Sr. ASIC Design Engineer (Silicon Engineering) - job 1 of 4
Skills
- RTL implementation in Verilog/SystemVerilog
- Timing closure and synthesis flow experience
- Familiarity with HDL simulators and lint/formality tools
- ASIC/SoC integration and silicon bring-up experience
- Knowledge of bus protocols (AXI, AHB, etc.) and embedded processors
- High-speed and low-power design techniques
- Scripting for flows (Python, TCL)
- Experience with FPGA toolchains (Vivado, Quartus) and EDA tools (VCS, Questa, IES, Spyglass)
Responsibilities
- Evaluate architectural trade-offs based on feature, performance, and system constraints
- Define micro-architecture and implement RTL in Verilog/SystemVerilog
- Integrate IP into top-level designs and deliver fully verified, synthesis/timing-clean implementations
- Collaborate with verification teams to ensure comprehensive test coverage
- Provide timing constraints and support physical implementation (synthesis, timing closure, formality)
- Participate in silicon bring-up and hardware validation
Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science required
- Advanced degree (MS/PhD) in related field is a plus
Benefits
- Base salary plus eligibility for equity/stock options and long-term incentives
- Potential discretionary bonuses and Employee Stock Purchase Plan
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short- and long-term disability insurance and life insurance
- Paid parental leave, vacation (approximately 3 weeks), and paid holidays
- Sick leave (exempt employees eligible for 5 days/year) and various employee discounts
Average salary estimate
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