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SpaceX is looking for a Sr. ASIC Design Engineer to architect and implement RTL for next-generation ASICs and FPGAs that will power Starlink’s space and ground systems.

Experienced FPGA Engineer needed to drive FPGA architecture and high-speed digital designs for state-of-the-art broadcast video and audio systems in a collaborative, remote-friendly environment.

Mission Driven

Social Impact Driven

Passion for Exploration

Reward & Recognition

SpaceX’s Starlink engineering team is hiring an FPGA/ASIC Engineer to develop and validate next-generation SoCs and FPGA designs for space and ground deployments using SystemVerilog/Verilog/VHDL.