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FPGA/ASIC Engineer (Silicon Engineering)

SpaceX’s Starlink team is developing the world’s largest satellite broadband system and is seeking an FPGA/ASIC engineer to design next-generation SoC blocks and integrate FPGA/ASIC solutions for space and ground infrastructure. The role involves full lifecycle RTL design, optimization for power/performance/area, lab bring-up, validation, and close collaboration with systems, firmware, backend and product teams.

Skills

  • RTL design with SystemVerilog/Verilog or VHDL
  • ASIC/FPGA system integration and SoC partitioning
  • Familiarity with EDA tool flows (simulators, lint, synthesis, FPGA tools)
  • Experience with DSP or digital communications datapaths and modem blocks
  • Proficiency in scripting/programming (Python, C/C++, Bash)
  • Hardware bring-up and lab debug using oscilloscopes, spectrum analyzers, and PCBs

Responsibilities

  • Design ASICs and FPGAs implementing complex SoC blocks and integration tasks using Verilog/SystemVerilog
  • Optimize designs for power, performance, and area
  • Participate in full ASIC/FPGA design lifecycle from architecture and microarchitecture to implementation and lab bring-up
  • Develop test system architectures and validation strategies for FPGA/ASIC verification, generational interoperability, and DSP/comm subsystem integration
  • Build tools and processes to analyze on-orbit and lab data to drive design improvements
  • Collaborate with software engineers to develop production software for hardware designs

Education

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or related field (required)
  • Master’s in Electrical/Computer Engineering or related field (preferred)

Benefits

  • Base salary within disclosed ranges plus potential long-term incentives (stock/options) and discretionary bonuses
  • Comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan access
  • Short & long-term disability and life insurance
  • Paid parental leave, paid vacation (approx. 3 weeks) and 10+ paid holidays
  • Sick leave for exempt employees and various employee discounts
  • Opportunity to work on space-grade, high-impact hardware for global connectivity
To read the complete job description, please click on the ‘Apply’ button
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Average salary estimate

$146250 / YEARLY (est.)
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$122500K
$170000K

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FUNDING
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SENIORITY LEVEL REQUIREMENT
TEAM SIZE
SALARY RANGE
$122,500/yr - $170,000/yr
EMPLOYMENT TYPE
Full-time, onsite
DATE POSTED
November 27, 2025
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