Asic Jobs
Browse 47 exciting jobs hiring in Asic now. Check out companies hiring such as NVIDIA, SpaceX, Advanced Technology Services in Sioux Falls, Tucson, Mesa.
Lead development of AI-driven timing and constraint sign-off solutions that integrate timing tools, knowledge graphs, and agentic orchestration to accelerate sign-off on NVIDIA silicon.
NVIDIA is hiring a Field Applications Engineer to support Cisco’s integration and deployment of NVIDIA switch ASICs and networking platforms through hands-on debugging, SDK onboarding, and technical enablement.
Be part of SpaceX’s Radiation Effects team in Orlando to develop, automate, and execute radiation tests that validate avionics hardware for extreme space environments.
Work with a fast-moving AI hardware team to design and optimize custom accelerators and SoC solutions that power next-generation machine learning systems.
Work on next-generation AI accelerators and SoC solutions, designing and optimizing hardware to power high-performance machine learning systems in a remote, collaborative environment.
An engineering role to design and optimize AI-focused hardware (FPGA/ASIC/SoC) and integrate accelerators with software and research teams to enable high-performance machine learning systems.
Lead DFT strategy and ATPG lifecycle development at NVIDIA to enable world-class test architectures for large-scale, multi-chiplet silicon platforms.
Palo Alto Networks is hiring a Senior System Software Engineer to architect and prototype ASIC/FPGA-based system solutions and develop low-level software and tooling for next-generation firewall platforms.
Etched is hiring a Manufacturing Electrical Engineer in San Jose to lead board-level NPI, DFM, and yield optimization for its transformer-optimized AI ASIC systems.
Experienced component engineering professional needed to lead component selection, qualification, and supplier risk mitigation for Palo Alto Networks’ hardware products at our Santa Clara headquarters.
Senior ASIC Verification Engineer role at NVIDIA to lead verification of global IP using SystemVerilog/UVM, coverage-driven methodologies, and automation across multiple product domains.
Lead silicon architecture and delivery at Voyant Photonics as VP of Silicon Engineering, owning multi-project ASIC development from architecture through volume production to enable next-generation compact FMCW LiDAR.
Intel CEG is hiring a Senior Director to lead SERDES architecture, mixed-signal design, and cross-functional integration for high-speed I/O IP across advanced process nodes.
Lead and execute DFX programs at NVIDIA to accelerate tape-out cycles and optimize testability for next-generation GPUs and SoCs.
Palo Alto Networks is hiring a Senior Component Engineer to lead component selection, qualification, and supplier-driven quality improvement for its Santa Clara hardware programs.
Medtronic is hiring a Distinguished Engineer in Tempe to lead ultra-low-power SoC/ASIC architecture, analog design flows and verification across cross-functional teams to advance medical device innovations.
Intel Central Engineering Group is hiring a Senior Silicon Design Engineer to lead RTL-to-GDS physical implementation, timing and power closure, and verification/signoff for complex SoC and IP designs.
NVIDIA seeks an experienced Director of SoC IP RTL to lead RTL/IP teams and deliver high-performance, production-ready custom silicon across cloud, networking and ML product lines.
NVIDIA seeks a Senior ASIC Verification Engineer in Austin to lead verification of SoCs/GPUs—focusing on memory subsystems, firmware interactions, and advanced verification methodologies.
NVIDIA is hiring a Senior Video ASIC Design Engineer to architect and implement video IP for next-generation SoCs, driving design quality and performance alongside cross-functional teams.
Work on the chip simulation team to design and maintain high-accuracy simulators and debugging tools that enable development of Etched's Sohu transformer ASIC software stack.
Experienced electrical engineer needed to lead troubleshooting, obsolescence management, and value-engineering for medical ultrasound electronics at FUJIFILM Sonosite in Bothell.
Applied Machine Learning Engineer (New Grad 2025) to apply ML and data science to VLSI circuit design, pre-/post-silicon analysis, and layout optimization at NVIDIA’s Santa Clara site.
Senior Technologist to lead end-to-end ASIC/SoC development for SanDisk storage controllers, providing technical authority, risk management, and cross-functional leadership.
Etched seeks a Post-Silicon Validation Engineer to lead silicon bring-up and system-level validation of cutting-edge AI accelerator SoCs at our Santana Row San Jose headquarters.
OpenAI’s Hardware team is hiring a Strategic Sourcing & Partnerships Manager to lead EDA/IP, emulation, and ASIC supplier strategy, contracting, and vendor partnerships for next-generation AI silicon.
Early-career CAD Engineer to drive standard cell development, automation, and DFM practices for NVIDIA's cutting-edge physical design teams in Santa Clara.
NVIDIA is hiring a Senior Package Layout Engineer to design and optimize high-speed, high-density ASIC package substrates in a hybrid Santa Clara role.
Lead development and validation of high-speed SerDes for Starlink ASICs, collaborating across design, validation, and software teams to ensure reliable serial links in space and ground applications.
NVIDIA is hiring a Senior ASIC Physical Design Engineer (Netlisting) to drive netlist quality, equivalence checking, CDC analysis and timing closure for high-performance CPU/GPU/SoC designs.
NVIDIA is recruiting first- and second-year undergraduates for a 12-week, on-site Ignite Hardware Engineering internship in Santa Clara to work on real GPU, ASIC, and hardware infrastructure projects.
SpaceX is hiring a Physical Design Engineer to work on ASIC physical implementation and signoff for next-generation Starlink silicon.
Build high-performance ML compiler technology at Mythic to map deep learning workloads onto a novel analog dataflow accelerator while influencing hardware–software co-design.
Senior RTL architect needed to lead digital design and backend implementation for high-performance memory interface ASICs at Renesas's Duluth hybrid office.
Lead lab development and validation of LiDAR and camera imaging technologies for vehicle applications as an Advanced Optical Sensor Test Engineer at General Motors.
NVIDIA is hiring an EDA Workflow Optimization Engineer to investigate and optimize end-to-end chip-design workflows, build reliable metrics and infrastructure, and enable engineers to develop at high velocity.
NVIDIA is hiring an entry-level ASIC Design Engineer in Santa Clara to implement and verify RTL for GPUs and SoCs, contributing to high-performance silicon designs.
SanDisk seeks a Senior Product Development Engineer in Milpitas to lead PCIe/NVMe SSD system test, qualification and production-readiness efforts.
Experienced Quality Engineer wanted to lead QA processes and supplier quality for Etched’s advanced AI hardware production at our San Jose headquarters and partner factories.
Lead the architecture, RTL implementation, simulation, and verification of FPGA/ASIC solutions for high-reliability electronic control systems in a hybrid role requiring U.S. citizenship.
Experienced electrical engineer needed to design and validate high-performance avionics and high-speed PCBAs for next-generation autonomous air vehicles at Anduril's Costa Mesa team.
Lead materials lifecycle and supplier execution for Etched’s server and rack hardware, ensuring material readiness from NPI through high-volume production.
NVIDIA is hiring a VLSI CAD Engineer in Santa Clara to develop and maintain scalable EDA/CAD flows and automation that speed development of next-generation AI chips.
Syntiant is hiring a seasoned SoC Design Engineer to drive microarchitecture, RTL implementation, verification, low-power design and silicon bring-up for the next-generation Neural Decision Processor.
Senior FPGA/ASIC engineer needed to architect and verify complex RTL-based designs for high-reliability electronic control systems in a hybrid U.S. role requiring citizenship.
Senior Design Verification Engineer needed to lead digital ASIC verification for Starlink's next-generation space and ground chips at SpaceX's Sunnyvale engineering team.
Experienced ASIC design verification engineer needed to lead block- and system-level verification for Starlink ASICs, supporting pre-silicon verification through post-silicon validation at SpaceX.
How much do asic jobs pay?
Below 50k*
0
|
50k-100k*
1
|
Over 100k*
43
|
Top companies hiring for asic jobs
