About the Group:
Client Engineering Group (CEG) oversees all test chip design, all foundational and hard IP, all EDA and design platform functions for Intel Products, as well as all external IP and EDA commercial licensing. As part of this new charter, CEG will also create a new business focused on providing custom ASIC design services for external customers.
About the Role:
Intel’s Client Engineering Group is seeking a technically strong and visionary lead for SERDES. This role will be responsible for driving the development and integration of high-speed I/O IP, including PCIe, Ethernet, and custom SERDES solutions, across advanced process nodes. The ideal candidate will have deep expertise in mixed-signal design, a proven track record of leading engineering teams, and the ability to collaborate across cross-functional groups to deliver best-in-class IP.
Key Responsibilities:
Technical Leadership
Lead the architecture, design, and validation of SERDES IP blocks across multiple generations of Intel process technologies.
Guide the team through all phases of development: specification, design, verification, silicon bring-up, and productization.
Ensure compliance with industry standards (e.g., IEEE 802.3, OIF CEI) and internal quality metrics.
Team Management
Build and mentor a high-performing team of analog/mixed-signal engineers.
Foster a culture of innovation, accountability, and continuous improvement.
Build and lead a global team.
Cross-Functional Collaboration
Work closely with SoC design, packaging, validation, and manufacturing teams to ensure seamless integration of SERDES IP.
Partner with customer engineering and product teams to translate customer requirements into technical deliverables
Program Execution
Own project schedules, deliverables, and risk mitigation plans.
Drive execution excellence and ensure timely delivery of IP to internal and external customers.
Required Experience:
Proven leadership experience managing technical teams.
Excellent communication and stakeholder management skills.
Familiarity with a variety of EDA tools
Strong understanding of semiconductor device physics and process technologies.
Preferred Skills
Experience with advanced packaging and signal/power integrity.
MS or PhD in Electrical Engineering or related field.
10+ years of experience in analog/mixed-signal IC design, with a focus on SERDES.
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$247,810.00-349,850.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.
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