Physical Design Engineer (Silicon Engineering)
Skills
- Hands-on experience with ASIC physical design and signoff flows
- Familiarity with industry EDA tools and their algorithms
- Static timing analysis and timing closure experience
- Scripting ability (bash, Python, TCL, Perl, Makefile)
- Understanding of CMOS/FinFET device behavior, power, and leakage
Responsibilities
- Perform partition synthesis and full physical implementation flow (synthesis, floorplanning, power/ground grid, place & route, timing, noise, physical verification).
- Drive signoff closure including STA, electromigration, voltage drop, noise analysis, and logic equivalency checks.
- Develop and improve physical design methodologies, automation scripts, and flows.
- Collaborate with ASIC design, architecture, firmware, and validation teams to set timing/power/area targets and explore RTL tradeoffs.
- Identify and resolve design, timing, and congestion issues and drive execution of fixes.
- Run, debug, and remediate signoff failures across standard signoff tools and flows.
Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (required)
Benefits
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Long-term incentives: stock, options, or long-term cash awards
- Employee Stock Purchase Plan (discounted stock purchase)
- Disability and life insurance
- Paid parental leave
- Approximately 3 weeks paid vacation and 10+ paid holidays
- 5 days sick leave for exempt employees
- Various employee discounts and perks
Average salary estimate
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