Dft Jobs
Browse 25 exciting jobs hiring in Dft now. Check out companies hiring such as Radical AI, NVIDIA, UChicago in Grand Rapids, Fort Worth, Washington.
Radical AI is hiring a Computational Materials Scientist to lead DFT and multiscale simulations for metal alloys, enabling AI-driven materials discovery and high-throughput computational workflows.
Lead the architecture, design, and verification of DFT IPs for NVIDIA's next-generation SoC products as a Senior ASIC Design Engineer specializing in DFX.
University of Chicago and Fermilab seek an Application Engineer to develop and support 3D IC design flows, provide EDA tool training, and coordinate MPW and packaging runs for the ACE-3D initiative.
EAG Laboratories seeks a Senior ATE Test Engineer to own SoC test strategy, develop ATE programs and hardware, and drive production readiness for mixed-signal/high-speed silicon in our Santa Clara lab.
Lead DFT strategy and ATPG lifecycle development at NVIDIA to enable world-class test architectures for large-scale, multi-chiplet silicon platforms.
NVIDIA is hiring a Senior DFX Methodology Engineer to architect and deploy advanced DFT methodologies (JTAG, I1500, I1687, BIST, scan) for high‑performance GPU products.
NVIDIA seeks a Senior DFT Methodology Engineer to architect next-generation in-system test solutions and lead validation efforts for advanced GPU and chiplet-based designs.
Lead and execute DFX programs at NVIDIA to accelerate tape-out cycles and optimize testability for next-generation GPUs and SoCs.
Intel Central Engineering Group is hiring a Senior Silicon Design Engineer to lead RTL-to-GDS physical implementation, timing and power closure, and verification/signoff for complex SoC and IP designs.
Work on next-generation GPU hardware at NVIDIA as an early-career Circuit Design Engineer focused on transistor-level design, low-power circuits, and system-level performance improvements.
Lead the design and implementation of manufacturing test solutions for NVIDIA datacenter systems, applying HW/SW expertise to improve automation, diagnostics, and production quality.
Senior Technologist to lead end-to-end ASIC/SoC development for SanDisk storage controllers, providing technical authority, risk management, and cross-functional leadership.
Lawrence Livermore National Laboratory is hiring graduate-level interns for a virtual Computational Chemistry and Materials Science summer program to perform simulation-based research and data analysis.
NVIDIA seeks a Senior System Test Engineer to design and implement manufacturing test solutions and automation for datacenter systems, leveraging HW/SW expertise to improve production quality and efficiency.
NVIDIA seeks a Senior Board Test Engineer to design and automate manufacturing test solutions for data center GPU/CPU boards and systems.
Intuitive is hiring a Sr Production Supervisor to lead high-volume medical device production teams in Sunnyvale, driving quality, efficiency, and continuous improvement.
Rambus is hiring an MTS Digital Engineering in San Jose to develop RTL, support functional/post‑layout simulation and lead chip bring‑up and validation for memory interface products.
NVIDIA is hiring a Senior ASIC Physical Design Engineer (Netlisting) to drive netlist quality, equivalence checking, CDC analysis and timing closure for high-performance CPU/GPU/SoC designs.
SpaceX is hiring a Physical Design Engineer to work on ASIC physical implementation and signoff for next-generation Starlink silicon.
Senior RTL architect needed to lead digital design and backend implementation for high-performance memory interface ASICs at Renesas's Duluth hybrid office.
SanDisk seeks a Senior Product Development Engineer in Milpitas to lead PCIe/NVMe SSD system test, qualification and production-readiness efforts.
Experienced electrical engineer sought to lead PCB design, validation, and production support for high-performance mixed-signal products in Melbourne, FL.
Syntiant is hiring a seasoned SoC Design Engineer to drive microarchitecture, RTL implementation, verification, low-power design and silicon bring-up for the next-generation Neural Decision Processor.
Experienced Electrical Test Engineer sought to develop and execute PCB test plans, diagnose failures, and implement test automation to support production and NPI at our Melbourne, FL engineering lab.
Principal RF Analog Sustaining Engineer I at CesiumAstro — hands-on production role focused on RF/microwave troubleshooting, root-cause analysis, and improving manufacturability and test methods.
