Tcl Jobs
Browse 20 exciting jobs hiring in Tcl now. Check out companies hiring such as NVIDIA, UChicago, Altera in Honolulu, Huntington Beach, Fayetteville.
Lead DFT architecture, implementation, and verification for NVIDIA’s next-generation SoCs as a Senior ASIC Design Engineer focused on design-for-test (DFX).
University of Chicago and Fermilab seek an Application Engineer to develop and support 3D IC design flows, provide EDA tool training, and coordinate MPW and packaging runs for the ACE-3D initiative.
Lead Altera’s SerDes Validation and Applications organization to drive first-time silicon success and customer adoption of high-speed serial IP across product lines.
NVIDIA is hiring a Senior DFX Methodology Engineer to architect and deploy advanced DFT methodologies (JTAG, I1500, I1687, BIST, scan) for high‑performance GPU products.
NVIDIA seeks a Senior DFT Methodology Engineer to architect next-generation in-system test solutions and lead validation efforts for advanced GPU and chiplet-based designs.
Lead formal verification efforts for cutting-edge CPU and HPC chip designs, applying advanced formal techniques, abstractions, and scripting to ensure functional correctness.
Shriners Children's seeks an Interface Analyst I to develop, monitor, and support healthcare system integrations (Cerner, Epic, Cloverleaf) while providing operational support and participating in on-call rotations.
Intel Central Engineering Group is hiring a Senior Silicon Design Engineer to lead RTL-to-GDS physical implementation, timing and power closure, and verification/signoff for complex SoC and IP designs.
Senior Formal Verification Engineer role at NVIDIA to design and implement formal verification flows and proofs for high-performance CPU/GPU silicon.
Work on next-generation GPU hardware at NVIDIA as an early-career Circuit Design Engineer focused on transistor-level design, low-power circuits, and system-level performance improvements.
Intel is hiring a technically strong CPU Backend Engineer to lead full-chip timing convergence, STA verification, and cross-functional collateral handoffs for future CPU designs.
Micron is hiring an HBM Memory Design Engineer intern to help design, simulate, and validate digital and analog circuits for next-generation High Bandwidth Memory at the Richardson, TX site.
Early-career CAD Engineer to drive standard cell development, automation, and DFM practices for NVIDIA's cutting-edge physical design teams in Santa Clara.
NVIDIA is hiring a Senior ASIC Physical Design Engineer (Netlisting) to drive netlist quality, equivalence checking, CDC analysis and timing closure for high-performance CPU/GPU/SoC designs.
SpaceX is hiring a Physical Design Engineer to work on ASIC physical implementation and signoff for next-generation Starlink silicon.
Drive EDA automation and ADK development for advanced semiconductor 3DHI and IC design workflows at the Texas Institute for Electronics.
Lead and execute SI/PI and multiphysics simulation and modeling efforts to enable advanced 2.5D/3D chiplet and multi-material package design at the Texas Institute for Electronics.
Lead the architecture, RTL implementation, simulation, and verification of FPGA/ASIC solutions for high-reliability electronic control systems in a hybrid role requiring U.S. citizenship.
NVIDIA is hiring a VLSI CAD Engineer in Santa Clara to develop and maintain scalable EDA/CAD flows and automation that speed development of next-generation AI chips.
Senior FPGA/ASIC engineer needed to architect and verify complex RTL-based designs for high-reliability electronic control systems in a hybrid U.S. role requiring citizenship.
