Browse 4 exciting jobs hiring in Timing Closure now. Check out companies hiring such as Marvell, Cadence, Intel in Glendale, Chesapeake, Columbus.
Lead micro-architecture and RTL development for high-performance, timing-critical DSP and connectivity designs at a global semiconductor company.
Cadence is hiring a Principal Application Engineer in digital implementation and signoff to partner with customers, drive tool adoption, and influence product direction.
Lead RTL development and SoC-level IP integration as a Principal Engineer in Intel's Client Engineering Group, shaping architecture, verification, and delivery across CPU/GPU/NOC and advanced compute projects.
Drive RTL-to-GDS physical implementation and signoff for custom Xeon-based SoCs in Intel's Data Center Group, focusing on timing closure, power optimization, and manufacturability.
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