Physical Design Jobs
Browse 13 exciting jobs hiring in Physical Design now. Check out companies hiring such as Intel, Cadence, KPFF Consulting Engineers in Madison, Des Moines, Aurora.
Intel seeks an entry-level SoC Design Engineer to perform RTL-to-GDS physical implementation, timing/power signoff, and design optimization for data-center SoC products.
Cadence is hiring a Principal Application Engineer in digital implementation and signoff to partner with customers, drive tool adoption, and influence product direction.
KPFF seeks a Protective Design Project Engineer in Portland to apply and expand structural protective-design expertise on resilience-focused projects across aviation, aerospace, manufacturing, and industrial sectors.
Intel's Silicon Engineering Group seeks a Physical Design Engineer to drive RTL-to-GDS implementation, timing/power closure, and verification for high-performance CPU cores.
Contribute to TEECOM's security discipline by designing, coordinating, and documenting physical and electronic security systems for healthcare and critical facilities while developing under mentorship in a fast-growing consulting practice.
Drive RTL-to-GDS physical implementation and signoff for custom Xeon-based SoCs in Intel's Data Center Group, focusing on timing closure, power optimization, and manufacturability.
Lead RTL feature development and verification for a breakthrough, ultra-low-power general-purpose processor at a fast-growing hardware startup.
NVIDIA seeks a CPU Design Methodology Engineer in Hillsboro, OR to lead SOC design automation, RTL integration, and front-end quality processes for advanced CPU projects.
Senior ASIC Design Engineer to develop high-performance, low-latency Switch Silicon RTL and deliver production-ready, timing-clean designs at NVIDIA's Santa Clara engineering team.
Work as a summer Software Intern at Cadence to develop and optimize placement algorithms in the Innovus Digital Implementation System under mentor guidance.
Lead development of RTL2GDSII methodology and physical design/CAD flows for multimillion-gate SoCs to enable high-performance, space-qualified silicon for Starlink.
Microchip Technology seeks a Principal Engineer (Applications, Physical Layer) in Austin to lead PHY development, validation and customer-facing debugging for market-leading semiconductor products.
Contribute to the design and implementation of high-performance, low-power CPUs at NVIDIA’s Hillsboro team, supporting AI, automotive, and consumer products.
