Senior Digital Design Engineer
Skills
- RTL design and feature implementation (Verilog/SystemVerilog)
- Full digital flow experience with EDA tools (Cadence, Synopsys, Siemens/Mentor, ANSYS)
- Pre-silicon verification and testbench development
- Memory subsystem design and memory compiler toolchains
- Vendor IP integration and IP interfacing
- Experience with silicon tape-outs and FPGA bring-up
- Familiarity with continuous integration for hardware
- Version control and scripting (Python preferred)
- Strong documentation and cross-team communication
Responsibilities
- Own feature development from specification through RTL design, implementation, and synthesis
- Implement product features for both silicon and FPGA platforms
- Develop unit testbenches and contribute to verification strategy and infrastructure
- Design and integrate memory subsystems and memory macros (SRAM, MRAM, etc.)
- Integrate vendor-provided IP with custom RTL and manage IP interfaces
- Use industry-standard EDA tools across the full digital design flow
- Collaborate with physical design to resolve RTL issues and ensure high-quality tape-out
- Partner with verification, software, and compiler teams to implement cross hardware–software features
- Produce high-quality design documentation and participate in reviews
- Mentor junior engineers and contribute to best-practice development processes
Education
- Bachelor’s degree required in EE, CS, or related field
- Master’s or PhD preferred
- Extensive hands-on post-graduate digital design experience (10+ years)
Benefits
- Competitive salary and meaningful equity
- 401(k) match and company-paid benefits
- Comprehensive health insurance
- Paid parental leave
- Flexible work arrangements (remote/hybrid)
- Professional development and growth opportunities
Average salary estimate
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