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Browse 11 exciting jobs hiring in Systemverilog now. Check out companies hiring such as Palo Alto Networks, Intuitive, Aetherflux in Little Rock, Greensboro, Baltimore.

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Lead ASIC design verification efforts at Palo Alto Networks, architecting and executing coverage-driven verification across simulation, emulation, formal, and silicon validation to deliver secure, high-performance ASICs to production.

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Posted 6 days ago

Lead architecture and implementation of high-performance FPGA-based image/video processing pipelines for Intuitive’s robotic imaging systems, collaborating with vision and EE teams to deliver low-latency, production-grade solutions.

Posted 6 days ago

Develop and validate high-performance, radiation-tolerant FPGA designs for Aetherflux's space-based power and communications systems.

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Mission Driven
Social Impact Driven
Passion for Exploration
Reward & Recognition

SpaceX’s Starlink engineering team is hiring an FPGA/ASIC Engineer to develop and validate next-generation SoCs and FPGA designs for space and ground deployments using SystemVerilog/Verilog/VHDL.

Logos Space Hybrid Mountain View or San Diego
Posted 15 days ago

Lead the architecture, design and delivery of FPGA-hosted DSP and transceiver IP for Logos Space's LEO satellite payloads and terminals, from concept to production.

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Inclusive & Diverse
Rise from Within
Mission Driven
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Customer-Centric
Snacks
Onsite Gym
Family Coverage (Insurance)
Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Resources
Life insurance
Disability Insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
Learning & Development
Paid Time-Off
401K Matching
Maternity Leave
Paternity Leave

Lead RTL development and SoC-level IP integration as a Principal Engineer in Intel's Client Engineering Group, shaping architecture, verification, and delivery across CPU/GPU/NOC and advanced compute projects.

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Posted 19 days ago

CesiumAstro is hiring an FPGA Verification Engineer II to develop UVMf testbenches, verification infrastructure, and CI/regression flows for advanced phased-array space communication systems in Westminster, CO.

Efficient Computer Hybrid San Jose, CA OR Pittsburgh, PA OR Remote
Posted 21 days ago

Lead RTL feature development and verification for a breakthrough, ultra-low-power general-purpose processor at a fast-growing hardware startup.

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Posted 23 days ago
Customer-Centric
Mission Driven
Inclusive & Diverse
Rise from Within
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Medical Insurance
Paid Time-Off
Maternity Leave
Mental Health Resources
Equity
Child Care stipend
Paternity Leave
WFH Reimbursements
Flex-Friendly
Dental Insurance
Vision Insurance
Life insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
401K Matching
Military leave

NVIDIA seeks a CPU Design Methodology Engineer in Hillsboro, OR to lead SOC design automation, RTL integration, and front-end quality processes for advanced CPU projects.

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NVIDIA Hybrid US, CA, Santa Clara
Posted 23 days ago
Customer-Centric
Mission Driven
Inclusive & Diverse
Rise from Within
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Medical Insurance
Paid Time-Off
Maternity Leave
Mental Health Resources
Equity
Child Care stipend
Paternity Leave
WFH Reimbursements
Flex-Friendly
Dental Insurance
Vision Insurance
Life insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
401K Matching
Military leave

Senior ASIC Design Engineer to develop high-performance, low-latency Switch Silicon RTL and deliver production-ready, timing-clean designs at NVIDIA's Santa Clara engineering team.

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Posted 29 days ago

CesiumAstro is hiring a Verification Engineer II in Austin to develop UVMf-based FPGA/digital verification infrastructure, drive CI/regression efforts, and mentor engineering teams for satellite phased-array systems.

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