Browse 19 exciting jobs hiring in Systemverilog now. Check out companies hiring such as Intel, Shield AI, USAA in St. Louis, Yonkers, Little Rock.
Lead SoC-level pre-silicon verification at Intel, owning strategy, execution, coverage closure and mentoring a team to drive first-silicon success.
Intel is seeking a Senior CPU Logic Design Engineer in Austin to lead RTL design, microarchitecture implementation, and verification for next-generation CPU cores.
Lead FPGA firmware development for high-performance communication and timing systems on Shield AI's next-generation autonomous UAV platform.
Shield AI is hiring a Staff FPGA Firmware Engineer to develop and verify high-performance FPGA communication and synchronization solutions for next-generation autonomous UAV platforms.
Lead a multidisciplinary hardware and firmware team to develop cutting-edge control systems for Atom Computing’s neutral-atom quantum computers.
Senior ASIC Verification Engineer role at NVIDIA to lead verification of global IP using SystemVerilog/UVM, coverage-driven methodologies, and automation across multiple product domains.
Lead formal verification efforts for cutting-edge CPU and HPC chip designs, applying advanced formal techniques, abstractions, and scripting to ensure functional correctness.
CesiumAstro is hiring a Senior FPGA Engineer II to design and verify high-speed FPGA networking systems for satellite and aerospace applications.
Intel Central Engineering Group is hiring a Senior Silicon Design Engineer to lead RTL-to-GDS physical implementation, timing and power closure, and verification/signoff for complex SoC and IP designs.
Senior Formal Verification Engineer role at NVIDIA to design and implement formal verification flows and proofs for high-performance CPU/GPU silicon.
NVIDIA seeks a Senior ASIC Verification Engineer in Austin to lead verification of SoCs/GPUs—focusing on memory subsystems, firmware interactions, and advanced verification methodologies.
Work on formal verification of high-performance RISC-V CPUs, fabrics, and accelerators, applying model checking and theorem proving to prove properties and uncover design issues.
Intel's Silicon Engineering Group seeks a SOC Design Engineer to develop and optimize CPU RTL, drive microarchitecture features, and collaborate on SoC integration and verification.
Rivos is hiring a Member of Technical Staff to lead pre-silicon functional verification of accelerator units and clusters using coverage-driven methodologies.
Senior Emulation Engineer needed to design, integrate, and optimize large-scale emulation and FPGA prototypes from RTL to accelerate verification and software bring-up within Intel's Silicon Engineering Group.
Lead FPGA architecture, design, verification, and system integration for the da Vinci Single Port surgical platform at Intuitive Surgical, owning FPGA solutions from concept to production.
Lead the architecture, RTL implementation, simulation, and verification of FPGA/ASIC solutions for high-reliability electronic control systems in a hybrid role requiring U.S. citizenship.
Syntiant is hiring a seasoned SoC Design Engineer to drive microarchitecture, RTL implementation, verification, low-power design and silicon bring-up for the next-generation Neural Decision Processor.
Senior FPGA/ASIC engineer needed to architect and verify complex RTL-based designs for high-reliability electronic control systems in a hybrid U.S. role requiring citizenship.
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