Browse 11 exciting jobs hiring in Systemverilog now. Check out companies hiring such as Palo Alto Networks, Intuitive, Aetherflux in Little Rock, Greensboro, Baltimore.
Lead ASIC design verification efforts at Palo Alto Networks, architecting and executing coverage-driven verification across simulation, emulation, formal, and silicon validation to deliver secure, high-performance ASICs to production.
Lead architecture and implementation of high-performance FPGA-based image/video processing pipelines for Intuitive’s robotic imaging systems, collaborating with vision and EE teams to deliver low-latency, production-grade solutions.
Develop and validate high-performance, radiation-tolerant FPGA designs for Aetherflux's space-based power and communications systems.
SpaceX’s Starlink engineering team is hiring an FPGA/ASIC Engineer to develop and validate next-generation SoCs and FPGA designs for space and ground deployments using SystemVerilog/Verilog/VHDL.
Lead the architecture, design and delivery of FPGA-hosted DSP and transceiver IP for Logos Space's LEO satellite payloads and terminals, from concept to production.
Lead RTL development and SoC-level IP integration as a Principal Engineer in Intel's Client Engineering Group, shaping architecture, verification, and delivery across CPU/GPU/NOC and advanced compute projects.
CesiumAstro is hiring an FPGA Verification Engineer II to develop UVMf testbenches, verification infrastructure, and CI/regression flows for advanced phased-array space communication systems in Westminster, CO.
Lead RTL feature development and verification for a breakthrough, ultra-low-power general-purpose processor at a fast-growing hardware startup.
NVIDIA seeks a CPU Design Methodology Engineer in Hillsboro, OR to lead SOC design automation, RTL integration, and front-end quality processes for advanced CPU projects.
Senior ASIC Design Engineer to develop high-performance, low-latency Switch Silicon RTL and deliver production-ready, timing-clean designs at NVIDIA's Santa Clara engineering team.
CesiumAstro is hiring a Verification Engineer II in Austin to develop UVMf-based FPGA/digital verification infrastructure, drive CI/regression efforts, and mentor engineering teams for satellite phased-array systems.
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