Verilog Jobs
Browse 28 exciting jobs hiring in Verilog now. Check out companies hiring such as CesiumAstro, NVIDIA, Jobgether in Durham, Augusta-Richmond County, Pembroke Pines.
CesiumAstro is hiring a Senior Verification Engineer I to lead FPGA/digital verification, build UVMf testbenches and CI-driven automation for space-grade phased array systems.
Lead DFT architecture, implementation, and verification for NVIDIA’s next-generation SoCs as a Senior ASIC Design Engineer focused on design-for-test (DFX).
Work with a fast-moving AI hardware team to design and optimize custom accelerators and SoC solutions that power next-generation machine learning systems.
Work on next-generation AI accelerators and SoC solutions, designing and optimizing hardware to power high-performance machine learning systems in a remote, collaborative environment.
An engineering role to design and optimize AI-focused hardware (FPGA/ASIC/SoC) and integrate accelerators with software and research teams to enable high-performance machine learning systems.
Apex is hiring a mid-level FPGA Engineer to develop and own flight-grade FPGA firmware that keeps satellite buses operating reliably in all mission scenarios.
Apex is hiring a Senior FPGA Engineer to design and own flight-grade FPGA firmware that keeps satellite buses operating reliably in all mission scenarios.
Lead formal verification efforts for cutting-edge CPU and HPC chip designs, applying advanced formal techniques, abstractions, and scripting to ensure functional correctness.
Support multidisciplinary biomedical research by designing and building embedded and RF prototypes, developing firmware, and validating sensor-based systems in a university lab environment.
Senior Formal Verification Engineer role at NVIDIA to design and implement formal verification flows and proofs for high-performance CPU/GPU silicon.
NVIDIA is hiring a Senior Video ASIC Design Engineer to architect and implement video IP for next-generation SoCs, driving design quality and performance alongside cross-functional teams.
Lead and mentor CAD and ESD engineering teams at Broadcom to deliver robust CAD flows and integrated ESD-protected IC designs.
Extropic is hiring an Embedded Design Engineer to develop FPGA RTL, low-level C++ firmware, and perform hands-on hardware bring-up for next-generation probabilistic hardware.
Intel's Silicon Engineering Group seeks a SOC Design Engineer to develop and optimize CPU RTL, drive microarchitecture features, and collaborate on SoC integration and verification.
Senior Emulation Engineer needed to design, integrate, and optimize large-scale emulation and FPGA prototypes from RTL to accelerate verification and software bring-up within Intel's Silicon Engineering Group.
Micron is hiring an HBM Memory Design Engineer intern to help design, simulate, and validate digital and analog circuits for next-generation High Bandwidth Memory at the Richardson, TX site.
Contribute to cutting-edge UAV avionics as an Embedded Engineering Co-op, writing C/C++ firmware and integrating systems across hardware, autonomy, and test teams at Shield AI in Boston.
Shield AI is hiring an Embedded Engineering Co-op in the Dallas area to develop C/C++ avionics firmware and integrate embedded systems for autonomous UAVs under senior-engineer mentorship.
Lead mixed-signal and analog circuit design for high-speed DRAM/SerDes memory I/O interfaces on NVIDIA's Santa Clara engineering team.
Rambus is hiring an MTS Digital Engineering in San Jose to develop RTL, support functional/post‑layout simulation and lead chip bring‑up and validation for memory interface products.
NVIDIA is recruiting first- and second-year undergraduates for a 12-week, on-site Ignite Hardware Engineering internship in Santa Clara to work on real GPU, ASIC, and hardware infrastructure projects.
Senior RTL architect needed to lead digital design and backend implementation for high-performance memory interface ASICs at Renesas's Duluth hybrid office.
Senior Software Engineer to design and implement high-performance C++/Golang tools for code analysis, coverage, and chip verification at NVIDIA's Santa Clara engineering organization.
NVIDIA is hiring an entry-level ASIC Design Engineer in Santa Clara to implement and verify RTL for GPUs and SoCs, contributing to high-performance silicon designs.
Lead FPGA architecture, design, verification, and system integration for the da Vinci Single Port surgical platform at Intuitive Surgical, owning FPGA solutions from concept to production.
Lead the architecture, RTL implementation, simulation, and verification of FPGA/ASIC solutions for high-reliability electronic control systems in a hybrid role requiring U.S. citizenship.
Senior FPGA/ASIC engineer needed to architect and verify complex RTL-based designs for high-reliability electronic control systems in a hybrid U.S. role requiring citizenship.
Arista Networks is hiring a Senior Hardware Design Engineer to lead high-speed PCB, SI/PI and system-level hardware design for next-generation 100G/200G Ethernet switching platforms.
How much do verilog jobs pay?
Below 50k*
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50k-100k*
6
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Over 100k*
21
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Top companies hiring for verilog jobs
Best cities to find verilog jobs
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