Browse 16 exciting jobs hiring in Verilog now. Check out companies hiring such as Marvell, Intuitive, Aetherflux in Oklahoma City, Fontana, Baltimore.
Lead micro-architecture and RTL development for high-performance, timing-critical DSP and connectivity designs at a global semiconductor company.
Lead architecture and implementation of high-performance FPGA-based image/video processing pipelines for Intuitive’s robotic imaging systems, collaborating with vision and EE teams to deliver low-latency, production-grade solutions.
Develop and validate high-performance, radiation-tolerant FPGA designs for Aetherflux's space-based power and communications systems.
Lead development and integration of embedded software for Intuitive's da Vinci surgical systems, working on low-level drivers, multi-processor communication, and system diagnostics to deliver high-quality medical device software.
Lead the design and first‑silicon delivery of ultra‑high‑speed (>20 GHz) CMOS ADCs and DACs that interface directly with an optical compute fabric for a rapidly scaling AI hardware company.
Experienced FPGA Engineer needed to drive FPGA architecture and high-speed digital designs for state-of-the-art broadcast video and audio systems in a collaborative, remote-friendly environment.
SpaceX’s Starlink engineering team is hiring an FPGA/ASIC Engineer to develop and validate next-generation SoCs and FPGA designs for space and ground deployments using SystemVerilog/Verilog/VHDL.
Lead the design and verification of advanced digital, analog, and power electronics including FPGA development and system-level integration for high-reliability products across multiple markets.
Lead the architecture, design and delivery of FPGA-hosted DSP and transceiver IP for Logos Space's LEO satellite payloads and terminals, from concept to production.
Lead the hardware architecture and development of high-performance electronic systems, driving digital/analog/power design and FPGA integration from concept to production.
CesiumAstro is hiring an FPGA Verification Engineer II to develop UVMf testbenches, verification infrastructure, and CI/regression flows for advanced phased-array space communication systems in Westminster, CO.
Lead RTL feature development and verification for a breakthrough, ultra-low-power general-purpose processor at a fast-growing hardware startup.
NVIDIA is hiring an ASIC Design Engineer to build and maintain hardware design tools, automated RTL generation workflows, and verification methodologies that scale across product teams.
NVIDIA seeks a CPU Design Methodology Engineer in Hillsboro, OR to lead SOC design automation, RTL integration, and front-end quality processes for advanced CPU projects.
Senior ASIC Design Engineer to develop high-performance, low-latency Switch Silicon RTL and deliver production-ready, timing-clean designs at NVIDIA's Santa Clara engineering team.
Lead embedded software design and implementation for advanced electrosurgical systems at Intuitive, using C/C++, Verilog and Python to deliver real-time data acquisition, control, and test solutions.
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