Browse 16 exciting jobs hiring in Rtl now. Check out companies hiring such as Palo Alto Networks, Intel, NVIDIA in Amarillo, Austin, San Diego.
Lead ASIC design verification efforts at Palo Alto Networks, architecting and executing coverage-driven verification across simulation, emulation, formal, and silicon validation to deliver secure, high-performance ASICs to production.
Intel seeks an entry-level SoC Design Engineer to perform RTL-to-GDS physical implementation, timing/power signoff, and design optimization for data-center SoC products.
NVIDIA is hiring a Senior GPU Power Architect to lead power modeling and hardware feature design that improves GPU efficiency for graphics and deep learning workloads.
Experienced Technical Program Manager needed to drive Design IP projects and customer engagements from conception through delivery at a leading EDA company.
Lead development of functional and cycle-accurate performance models and simulation tooling to steer architecture, software, and optical design decisions for a fast-growing AI systems company.
SpaceX’s Starlink engineering team is hiring an FPGA/ASIC Engineer to develop and validate next-generation SoCs and FPGA designs for space and ground deployments using SystemVerilog/Verilog/VHDL.
Intel's Silicon Engineering Group seeks a Physical Design Engineer to drive RTL-to-GDS implementation, timing/power closure, and verification for high-performance CPU cores.
Lead the architecture, design and delivery of FPGA-hosted DSP and transceiver IP for Logos Space's LEO satellite payloads and terminals, from concept to production.
Lead RTL development and SoC-level IP integration as a Principal Engineer in Intel's Client Engineering Group, shaping architecture, verification, and delivery across CPU/GPU/NOC and advanced compute projects.
Work remotely on industry-leading SoCs implementing and optimizing DFT solutions (SCAN, MBIST, BSCAN) from RTL through manufacturing to improve test coverage and reduce test cost.
Drive RTL-to-GDS physical implementation and signoff for custom Xeon-based SoCs in Intel's Data Center Group, focusing on timing closure, power optimization, and manufacturability.
Lead RTL feature development and verification for a breakthrough, ultra-low-power general-purpose processor at a fast-growing hardware startup.
NVIDIA is hiring an ASIC Design Engineer to build and maintain hardware design tools, automated RTL generation workflows, and verification methodologies that scale across product teams.
NVIDIA seeks a CPU Design Methodology Engineer in Hillsboro, OR to lead SOC design automation, RTL integration, and front-end quality processes for advanced CPU projects.
Senior ASIC Design Engineer to develop high-performance, low-latency Switch Silicon RTL and deliver production-ready, timing-clean designs at NVIDIA's Santa Clara engineering team.
CesiumAstro is hiring a Verification Engineer II in Austin to develop UVMf-based FPGA/digital verification infrastructure, drive CI/regression efforts, and mentor engineering teams for satellite phased-array systems.
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