Browse 33 exciting jobs hiring in Rtl now. Check out companies hiring such as Intel, Park Place Finance, Jobgether in Oakland, Minneapolis, Henderson.
Intel is seeking a Senior CPU Logic Design Engineer in Austin to lead RTL design, microarchitecture implementation, and verification for next-generation CPU cores.
Experienced Loan Processor sought for private lender to manage RTL, Bridge, Renovation, Ground-Up Construction, and DSCR loan files from application to closing with strong attention to compliance and communication.
Work on next-generation AI accelerators and SoC solutions, designing and optimizing hardware to power high-performance machine learning systems in a remote, collaborative environment.
An engineering role to design and optimize AI-focused hardware (FPGA/ASIC/SoC) and integrate accelerators with software and research teams to enable high-performance machine learning systems.
Lead DFT strategy and ATPG lifecycle development at NVIDIA to enable world-class test architectures for large-scale, multi-chiplet silicon platforms.
NVIDIA is hiring a Senior DFX Methodology Engineer to architect and deploy advanced DFT methodologies (JTAG, I1500, I1687, BIST, scan) for high‑performance GPU products.
NVIDIA seeks a Senior DFT Methodology Engineer to architect next-generation in-system test solutions and lead validation efforts for advanced GPU and chiplet-based designs.
Apex is hiring a mid-level FPGA Engineer to develop and own flight-grade FPGA firmware that keeps satellite buses operating reliably in all mission scenarios.
Drive revenue as a DSCR Loan Officer at Park Place Finance by originating and closing residential investment loans while delivering consultative service and managing the full sales pipeline.
Lead a multidisciplinary hardware and firmware team to develop cutting-edge control systems for Atom Computing’s neutral-atom quantum computers.
Senior ASIC Verification Engineer role at NVIDIA to lead verification of global IP using SystemVerilog/UVM, coverage-driven methodologies, and automation across multiple product domains.
Lead formal verification efforts for cutting-edge CPU and HPC chip designs, applying advanced formal techniques, abstractions, and scripting to ensure functional correctness.
Lead the ML roadmap and build agentic, production-ready systems that make chip designers dramatically more productive at a fast-growing Palo Alto AI startup.
Intel Central Engineering Group is hiring a Senior Silicon Design Engineer to lead RTL-to-GDS physical implementation, timing and power closure, and verification/signoff for complex SoC and IP designs.
NVIDIA seeks an experienced Director of SoC IP RTL to lead RTL/IP teams and deliver high-performance, production-ready custom silicon across cloud, networking and ML product lines.
Senior Formal Verification Engineer role at NVIDIA to design and implement formal verification flows and proofs for high-performance CPU/GPU silicon.
Work on formal verification of high-performance RISC-V CPUs, fabrics, and accelerators, applying model checking and theorem proving to prove properties and uncover design issues.
Work on the chip simulation team to design and maintain high-accuracy simulators and debugging tools that enable development of Etched's Sohu transformer ASIC software stack.
Extropic is hiring an Embedded Design Engineer to develop FPGA RTL, low-level C++ firmware, and perform hands-on hardware bring-up for next-generation probabilistic hardware.
Intel's Silicon Engineering Group seeks a SOC Design Engineer to develop and optimize CPU RTL, drive microarchitecture features, and collaborate on SoC integration and verification.
Rivos is hiring a Member of Technical Staff to lead pre-silicon functional verification of accelerator units and clusters using coverage-driven methodologies.
Senior Emulation Engineer needed to design, integrate, and optimize large-scale emulation and FPGA prototypes from RTL to accelerate verification and software bring-up within Intel's Silicon Engineering Group.
At NVIDIA, a Senior Circuit Design Engineer will lead transistor-level digital IP design and physical implementation to enable high-performance, low-power AI processors across the product line.
WHOOP is hiring a temporary Platform Designer to iterate on and elevate the research platform’s UX, create prototypes and multilingual templates, and support clinically compliant feature design.
Rambus is hiring an MTS Digital Engineering in San Jose to develop RTL, support functional/post‑layout simulation and lead chip bring‑up and validation for memory interface products.
NVIDIA is hiring a Senior ASIC Physical Design Engineer (Netlisting) to drive netlist quality, equivalence checking, CDC analysis and timing closure for high-performance CPU/GPU/SoC designs.
SpaceX is hiring a Physical Design Engineer to work on ASIC physical implementation and signoff for next-generation Starlink silicon.
Senior RTL architect needed to lead digital design and backend implementation for high-performance memory interface ASICs at Renesas's Duluth hybrid office.
Lead the AI roadmap and a growing ML team at a Palo Alto startup building agentic systems that speed up semiconductor design through RTL code generation and physical-design optimization.
NVIDIA is hiring an entry-level ASIC Design Engineer in Santa Clara to implement and verify RTL for GPUs and SoCs, contributing to high-performance silicon designs.
Lead the architecture, RTL implementation, simulation, and verification of FPGA/ASIC solutions for high-reliability electronic control systems in a hybrid role requiring U.S. citizenship.
Syntiant is hiring a seasoned SoC Design Engineer to drive microarchitecture, RTL implementation, verification, low-power design and silicon bring-up for the next-generation Neural Decision Processor.
Senior FPGA/ASIC engineer needed to architect and verify complex RTL-based designs for high-reliability electronic control systems in a hybrid U.S. role requiring citizenship.
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