Rtl Jobs
Browse 33 exciting jobs hiring in Rtl now. Check out companies hiring such as Axiad, Rivos, NVIDIA in Little Rock, Portland, Greensboro.
Lead RTL-driven FPGA design and system bring-up for a security-focused hardware platform at a fast-growing Silicon Valley company.
Work on microarchitecture and logic design verification for a CPU team, building testbenches and verification infrastructures using SystemVerilog, C++, and Python to validate functionality and performance.
NVIDIA is hiring a Senior Digital Design Engineer to drive front-end RTL/firmware development, synthesis and timing closure, and post-silicon bring-up for high-speed I/O and silicon photonics products.
Lead emulation strategy and infrastructure at Alphawave IP as a Staff Emulation Engineer, driving methodology, automation, and cross-functional support for complex SoC/ASIC projects.
NVIDIA is hiring a Senior Circuit Design Engineer to lead transistor-level and custom digital IP design for cutting-edge GPU and AI products.
Rivos seeks a Silicon Power Engineer to lead power modeling, analysis, and optimization across CPU/SoC blocks, partnering closely with architecture and design teams to drive PPA improvements.
Lead emulation strategy and hands-on infrastructure development for large-scale SoC/ASIC projects at Alphawave IP, optimizing platforms, automation, and cross-functional bring-up workflows.
Lead and grow Eliyan’s physical design organization to deliver advanced-node ASIC tapeouts that meet stringent power, performance, and area targets for next-generation AI and data center solutions.
Shape and lead the ML architecture at a seed-stage startup building agent-driven tooling to transform semiconductor design and deploy production-grade systems from day one.
Lead end-to-end FPGA RTL architecture and flight-ready firmware development for E-Space's LEO satellite avionics from our Saratoga office.
Contribute to NVIDIA’s hardware ASIC teams on a 12-week, full-time internship building and verifying RTL and physical-design solutions for next-generation accelerated computing products.
A paid, full-time 12-week hardware verification internship at NVIDIA in Santa Clara for students pursuing degrees in electrical or computer engineering to work on real verification and validation projects.
Lead a hands-on team delivering high-speed mixed-signal digital subsystems for Flux Computing's next-generation optical AI processors, driving first-time-right delivery and cross-functional execution.
Lead FPGA architecture, RTL development, and hardware bring-up to implement real-time DSP and control systems for a next-generation FMCW LiDAR product at a fast-moving silicon photonics startup.
SpaceX’s Starlink engineering team is hiring a Sr. ASIC/SoC Verification Engineer to lead digital verification efforts for advanced space- and ground-deployed ASICs.
Rivos Inc. is hiring an experienced SoC Fabric Architect to lead architecture and specification of on-chip and off-chip interconnects, cache-coherent and non-coherent protocols, and system-level fabric trade-offs for high-performance RISC-V platforms.
Whatnot is hiring a Localization Operations Manager to lead localization operations, manage vendors and translators, and ensure high-quality multilingual app experiences across web and mobile.
Senior ASIC Design Engineer role at NVIDIA focusing on mixed-signal and digital IP design to improve power and performance for next-generation GPUs.
SpaceX Starshield is hiring an FPGA Engineer to build and validate flight-ready FPGA designs for secure, high-throughput satellite systems.
Lead microarchitecture and RTL development for power management and debug features at Rivos, working across SoC teams to deliver high-performance, power-efficient RISC-V server solutions.
Lead the creation and review of product security architectures and pre-silicon vulnerability analysis for hardware and embedded systems at NXP's Oak Hill office.
Contribute to Intel's silicon engineering teams as an intern working on architecture, design, verification, and validation of advanced processors and platforms.
Undergraduate interns will join Intel's Silicon Hardware Engineering teams in Hillsboro to help design, verify, and validate next-generation processor and SoC technologies.
Work on RTL and micro-architecture for AI/ML and data-analytics accelerators, using SystemVerilog, architecture insight, and synthesis/physical-design awareness to deliver high-performance, low-power designs.
SpaceX is hiring a Senior ASIC Design Engineer to implement and verify RTL for next-generation ASICs/FPGAs that will expand Starlink's global connectivity capabilities.
Work with Intel's Silicon Hardware Engineering teams as an intern contributing to design, verification, validation and performance optimization of next-generation processors and platforms.
Work on multi-FPGA, low-latency hardware systems at Riverlane to implement QEC decoders, high-throughput data movement and low-latency interfaces as a Digital Design Engineer.
Lead and own verification strategy and implementation for cutting-edge DDR5/DDR6 memory data buffer chips at Renesas, driving quality, performance, and team mentorship.
Solidigm is hiring a 3D NAND IP Logic Design Engineer to design and verify SystemVerilog RTL, develop microcode-based NAND algorithms, and lead pre/post-silicon validation for next-gen memory products.
Work on Etched's SoC power flows to generate accurate power profiles, build automation for RTL/gate-level estimation, and support IR/thermal sign-off for high-performance AI ASICs.
Experienced GPU performance verification engineer needed to architect and execute pre-silicon performance verification, benchmarking, and analysis for Samsung's mobile GPU products.
A Senior Circuit Design Engineer role at NVIDIA focused on advanced processor circuit innovation, noise mitigation, and mentoring within a dynamic global team.
Renesas is hiring a Principal DSP/Control Engineer to architect and implement digital control loop subsystems for cutting-edge semiconductor products in Austin, TX.
