Principal ASIC Design Engineer (Silicon Engineering)
Skills
- Strong RTL implementation experience (Verilog/SystemVerilog)
- ASIC and FPGA design and development experience
- Timing closure, synthesis, and static timing analysis
- Experience with clock domain crossing and power optimization techniques
- Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processors
- Scripting for automation (Python, TCL)
- Experience with EDA tools (HDL simulators, lint tools, FPGA toolchains)
- Silicon bring-up and validation experience
Responsibilities
- Design digital ASICs and FPGAs for Starlink projects from micro-architecture through silicon bring-up
- Define micro-architecture and implement RTL in Verilog/SystemVerilog, integrate into top level
- Ensure fully verified, synthesis- and timing-clean designs in collaboration with verification teams
- Provide timing constraints and support physical implementation (synthesis, timing closure, formality)
- Participate in silicon bring-up and validation activities
- Evaluate architectural trade-offs for features, performance, power, and system constraints
Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science required
- Advanced degree (MS/PhD) in related field preferred
Benefits
- Base salary plus eligibility for long-term incentives (stock, options, or cash awards)
- Potential discretionary bonuses and Employee Stock Purchase Plan
- Comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- Short- and long-term disability insurance and life insurance
- Paid parental leave
- Approximately 3 weeks paid vacation and 10+ paid holidays per year
- Exempt employees: 5 days sick leave per year and various employee discounts
Average salary estimate
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