Let’s get started
By clicking ‘Next’, I agree to the Terms of Service
and Privacy Policy, and consent to receive emails from Rise
Jobs / Job page
STA Physical Design Engineer image - Rise Careers
Job details

STA Physical Design Engineer

Job Description

Role: STA Physical Design Engineer
Location: Irvine, CA-Yes, Remote option available, BUT 2-3 weeks work in Irvine, CA is mandatory
Interview Process: Phone/Skype
Job Type: Contract
 

Senior STA Engineer We're looking for a highly skilled Senior Static Timing Analysis (STA) Engineer with deep expertise in Signal Integrity (SI), Power Integrity (PI), Design for Manufacturing (DFM), and chip finishing. The ideal candidate will have a strong background in physical design (PD), excellent project management skills, and the ability to lead and mentor junior engineers.
_____________________________
Qualifications
• Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
• 5+ years of experience in STA closure for complex digital designs.
• Proven expertise in Signal Integrity (SI) and Power Integrity (PI) analysis, including understanding of crosstalk and IR drop effects.
• Solid knowledge of chip finishing methodologies, including timing sign-off and tape-out readiness checks.
• Familiarity with Design for Manufacturing (DFM) principles and their application in physical design.
• Experience with industry-standard EDA tools for STA (e.g., PrimeTime, Tempus).
• Strong understanding of physical design (PD) concepts, including floorplanning, placement, and routing.
• Excellent problem-solving, analytical, and debugging skills.
• Strong verbal and written communication skills with the ability to lead technical discussions and present complex information clearly.
• Experience with scripting languages (Tcl, Python, Perl) is a must.
• Experience with management skills like project planning, scheduling, and resource allocation is a plus.

Responsibilities
• Lead and execute STA closure for complex SoC designs, ensuring all timing constraints are met across multiple corners and modes.
• Perform comprehensive Signal Integrity (SI) and Power Integrity (PI) analysis to identify and resolve timing issues caused by signal coupling, IR drop, and ground bounce.
• Develop and implement chip finishing strategies, including ECO flows (Engineering Change Orders), to ensure designs are ready for tape-out.
• Drive Design for Manufacturing (DFM) initiatives by collaborating with the design and foundry teams to optimize the physical layout for manufacturability and yield.
• Work closely with the physical design (PD) team to provide guidance on timing-driven placement and routing.
• Develop and improve STA methodologies, scripts, and flows to increase efficiency and accuracy.
• Effectively communicate technical challenges, progress, and solutions to cross-functional teams and management.

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
• 5+ years of experience in STA closure for complex digital designs.
• Proven expertise in Signal Integrity (SI) and Power Integrity (PI) analysis, including understanding of crosstalk and IR drop effects.
• Solid knowledge of chip finishing methodologies, including timing sign-off and tape-out readiness checks.
• Familiarity with Design for Manufacturing (DFM) principles and their application in physical design.
• Experience with industry-standard EDA tools for STA (e.g., PrimeTime, Tempus).
 

Additional Information

All your information will be kept confidential according to EEO guidelines.

Average salary estimate

$180000 / YEARLY (est.)
min
max
$140000K
$220000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

Similar Jobs
Photo of the Rise User
Posted 6 hours ago

Senior Teamcenter PLM Solution Architect (remote contract) to design, implement, and integrate Teamcenter/Active Workspace solutions with CATIA and NX for enterprise engineering workflows.

Photo of the Rise User
Posted 21 hours ago

Peraton is hiring an experienced Systems Engineer Lead Associate to drive systems design, integration, verification, and analysis in support of FAA efforts to modernize the National Airspace System.

Photo of the Rise User

Lead a team building production-grade deep learning perception systems for real-world transit and street-safety applications at Hayden AI in San Francisco.

Photo of the Rise User
Hermeus Hybrid No location specified
Posted 13 hours ago

Work with Hermeus as a paid Spring 2026 engineering intern contributing to propulsion, structures, avionics, software or test efforts on cutting-edge high-speed aircraft.

Posted 7 hours ago

Voltai is hiring an Engineering Manager in Palo Alto to lead a focused engineering team delivering agentic AI systems and tools for semiconductor and electronics design.

Photo of the Rise User
Posted 2 hours ago

Relativity Space seeks a Senior Additive Simulation Engineer to lead development of process and structural simulation for metal additive manufacturing in support of rocket design and production.

Photo of the Rise User
Posted 8 hours ago

Hands-on internship supporting propulsion engine and test-stand operations for a venture-backed company developing high-Mach and hypersonic aircraft.

Posted 9 hours ago

Reframe Systems seeks a hands-on Manufacturing Engineer to scale our Andover microfactory through data-driven workcell design, factory layout optimization, and cross-functional project delivery.

Photo of the Rise User
Posted 6 hours ago

Senior Teamcenter PLM Solution Architect (remote contract) to design, implement, and integrate Teamcenter/Active Workspace solutions with CATIA and NX for enterprise engineering workflows.

SE.GI. Hybrid US | WA | Bellevue - 12011 Bel-Red Road
Posted 19 hours ago

TYLin seeks a Summer 2026 Bridge Engineering Designer Intern in Bellevue to assist engineering teams with modeling, drawings, quantity take-offs, and site support while developing practical bridge design skills.

Photo of the Rise User
Sigma Defense Hybrid No location specified
Posted 12 hours ago

Sigma Defense is hiring a Network Engineer to design and document Navy network topologies, develop SD-WAN/IP plans, and produce test documentation while engaging with program stakeholders.

SE.GI. Hybrid US | CA | Sacramento - 1545 River Park Drive
Posted 9 hours ago

Lead Bridge Engineer at TYLin in Sacramento responsible for steering complex bridge design and construction-support projects, managing client relationships, and mentoring a team of engineers.

Photo of the Rise User
Posted 8 hours ago

Lead and grow LaBella’s traffic engineering practice across Long Island and the NYC metro as a senior technical lead, client advisor, and business development driver working hybrid or remotely.

Photo of the Rise User
Posted 18 hours ago

Experienced Acoustics Engineer needed to lead noise analyses, modeling, and mitigation design for land development and infrastructure projects at Kimley-Horn's Philadelphia team.

PDDN is a provider of end-to-end software solutions and IT consulting Services and software development Company. is headquartered in Fremont, California with clients across the Silicon Valley and other Information technology Hubs in different stat...

4 jobs
MATCH
Calculating your matching score...
FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
EMPLOYMENT TYPE
Contract, hybrid
DATE POSTED
September 19, 2025
Risa star 🔮 Hi, I'm Risa! Your AI
Career Copilot
Want to see a list of jobs tailored to
you, just ask me below!