Job details

CPU Backend Engineer - Full-Chip Timing

Job Details:

Job Description:

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are
Become a key member of a team participating in the Integration and Verification of a future Intel CPU. This position requires and Engineer with broad Physical Design and Static Timing Analysis skills, coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team.

Who You Are

We are looking for a highly motivated and technically savvy experienced engineer to drive the timing convergence for Full-Chip models.

Responsibilities may include but are not limited to:

As a FC Design Engineer, you will perform constraints management and STA verification.
You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR.
You will drive timing closure and provide collateral for SOC drops.

Behavioral skills we are looking for:

Excellent written and oral presentation skills, and willing to work across multiple organizations and geographies.
Effective team player with continuous learning mindset.
Strong analytical and problem-solving skills.
Be willing to balance multiple tasks.
Self-starter with a collaborative spirit, comfortable asking for help when needed.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

The candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering or similar field with 4+ years' of relevant experience or Master’s Degree in Electrical Engineering, Computer Engineering or similar field with 3+ years' of relevant experience

Preferred Qualifications

Experience with Static Timing Analysis using PrimeTime
Experience with Scripting in one or more of the following languages (TCL, Perl, or Python)
Experience with verification of power crossing ie. VC-static (VC LP), UPF

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

Virtual US

Additional Locations:

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$139,710.00-262,680.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 10/09/2026

CPU Backend Engineer Static Timing Analysis PrimeTime Physical Design Timing Closure STA TCL Perl Python UPF Power Verification Full-Chip SoC Clocking Synthesis APR

Average salary estimate

$201195 / YEARLY (est.)

min

max

$139710K

$262680K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

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