Job Details:

Job Description: 

About the Group:
Central Engineering Group (CEG) oversees all test chip design, all foundational and hard IP, all EDA and design platform functions for Intel Products, as well as all external IP and EDA commercial licensing. As part of this new charter, CEG will also create a new business focused on providing custom ASIC design services for external customers.

About the Role:

The emulation engineer builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools.

Responsibilities:

• Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware.
• Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability.
• Enables acceleration of RTL development and improve emulation/FPGA model usability for pre-silicon verification, post-silicon validation, and software development.
• Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing pre-silicon verification environments, test suites, and methodologies for emulation efficiency.
• Develops and utilizes automation aids, flows, and scripts in support of emulation utilization.
• Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model).
• Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues.

Required Skills and Experience:

• Experience with emulators such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce for large scale designs
• Strong understanding of Computer architecture, design principles, validation methodologies and tools
• Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog based verification techniques.

Preferred Skills and Experience:

• Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environments.
• Experience in SW Programming/scripting and debug such as assembly, C, C++, Perl, Python

Qualifications:

• Bachelors degree in Electrical/Computer Engineering  or similar field (Masters preferred)
• 20+ years of experience working in Emulation domain

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Folsom

Additional Locations:

US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

 

 

Annual Salary Range for jobs which could be performed in the US:

 

 

$214,730.00-303,140.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.