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Job details

Design Engineer

Red Cell Partners, through its startup Claros, focuses on innovative semiconductor power management solutions improving AI compute efficiency. Claros seeks a detail-oriented Design Engineer experienced in ASIC digital design to contribute to PMIC development in a supportive, fast-paced, hybrid environment.

Skills

  • RTL coding using SystemVerilog
  • Hardware debugging with benchtop lab equipment (oscilloscopes, waveform generators, power supplies, logic analyzers)
  • ASIC design flow knowledge including RTL design, synthesis, timing closure, and verification
  • Experience with digital simulation tools (Xcelium, Questa, Vivado Simulator)
  • FPGA development and prototyping using Xilinx tools (Vivado, ISE)
  • Scripting for automation and test (Python, TCL, Perl)
  • Strong digital design fundamentals and hardware debugging skills
  • Effective communication and documentation skills
  • Proactive and detail-oriented work approach

Responsibilities

  • Design and implement digital blocks within PMICs using Verilog/SystemVerilog and standard ASIC design flows
  • Participate in pre-silicon simulation and verification using Cadence tools and standard cell libraries
  • Support ASIC tape-out activities including synthesis, static timing analysis, and design signoff
  • Develop FPGA-based test builds with Xilinx tools for post-silicon validation and characterization
  • Interface and integrate digital control logic with analog/mixed-signal blocks
  • Write and maintain automation scripts for regression testing, build flows, and hardware validation
  • Collaborate with cross-functional teams including analog designers, layout, validation, and test engineers

Education

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field

Benefits

  • Career advancement opportunities with company growth
  • 100% employer-paid comprehensive healthcare (medical, dental, vision) for employee and family
  • Paid maternity and paternity leave for 14 weeks at normal pay
  • Unlimited PTO with management approval
  • Professional development and continued learning opportunities
  • Optional 401K, FSA, and equity incentives
To read the complete job description, please click on the ‘Apply’ button
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Average salary estimate

$145000 / YEARLY (est.)
min
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$135000K
$155000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

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FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
SALARY RANGE
$135,000/yr - $155,000/yr
EMPLOYMENT TYPE
Full-time, hybrid
DATE POSTED
July 26, 2025
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