Do Something Wonderful!
Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
Do you want to collaborate with the best minds in the world? Do you love the idea of directly impacting Intel's future CPU generations? Come intern with our team this summer. In this graduate internship, you will be working alongside a World-class SOC design team within the Xeon Engineering Group (XEG) delivering on next-generation Xeon products for Server markets, with a focus on AI enabling SOCs.
Who You Are
This role is in the Physical Design Engineer. Your responsibilities will include, but are not limited to:
Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff include formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
Possesses CPU specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
Works intimately with industry EDA vendors to build and enhance tool capabilities to design a high speed, low power synthesizable CPU.
Optimizes CPU design to improve product level parameters such as power, frequency, and area.
Participates in the development and improvement of physical design methodologies and flow automation.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Bachelor's degree in electrical or computer engineering, or a related field, with a year of related experience OR Master's degree in electrical or computer engineering, or a related field.
Preferred Qualifications
At least 3+ months of experience with the following:
Experience with Fusion Compiler or Primetime
Design Automation tools, flows and methodology
Experience with VLSI hardware design or CMOS transistor level circuit fundamentals
Layout cleanup expertise DRCs, density, etc.
TCL, Python, Perl and/or C++ programming
Circuit design
Computer architecture
TL/Logic design Verilog, VCS, etc.
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$104,890.00-$148,080.00Salary range dependent on a number of factors including location and experience.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.
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