Design Verification Engineer (Silicon Engineering) - job 1 of 6
Skills
- SystemVerilog testbench development
- UVM and verification methodologies
- Constrained-random verification and coverage-driven verification
- Python scripting for automation
- MATLAB for test generation/analysis
- RTL understanding and chip bring-up familiarity
- Strong object-oriented programming and coding skills
- Regression and coverage closure workflows
Responsibilities
- Perform digital ASIC verification at block and system level
- Author and review test plans, develop test harnesses and test sequences
- Develop SystemVerilog testbench infrastructure (UVM and non-UVM), including DSP block verification
- Execute regressions, manage code and functional coverage closure
- Automate test generation and verification flows using Python and MATLAB
- Contribute to pre-silicon verification, chip bring-up, and post-silicon validation
- Collaborate with cross-disciplinary teams (architecture, firmware, implementation) to drive verification completeness
Education
- Bachelor’s degree in Electrical Engineering, Computer Science, or Computer Engineering (required)
- Advanced degree in Electrical/Computer Engineering preferred
Benefits
- Medical, vision, and dental coverage
- 401(k) retirement plan
- Short- and long-term disability insurance and life insurance
- Eligibility for equity/stock options and Employee Stock Purchase Plan
- Paid parental leave
- Approximately 3 weeks paid vacation and 10+ paid holidays per year
- Exempt employees eligible for 5 days sick leave per year
- Various employee discounts and perks
Average salary estimate
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