Browse 17 exciting jobs hiring in Silicon Validation now. Check out companies hiring such as NVIDIA, Etched, Advanced Technology Services in Irvine, San Diego, Nashville-Davidson.
NVIDIA is hiring a System Level Product Development Engineer in Santa Clara to drive SLT testing, characterization and yield improvements for advanced semiconductor products.
Senior engineer needed to drive system-level characterization, yield improvement, and post-silicon validation for NVIDIA's GPU/Tegra products in a cross-functional, high-performance environment.
Lead hardware validation and post-silicon characterization for Etched's ASIC platforms, owning PCB-level verification, margin analysis, and root-cause debugging to deliver production-quality systems.
Rambus is seeking a New College Grad Validation Engineer in San Jose to develop PMIC validation environments and support post-silicon bring-up for memory power solutions.
Rambus is hiring a Test Engineering Intern in San Jose to support DFT, wafer-sort, first-silicon bring-up, and test program development for advanced memory and silicon IP products.
Lead and scale NVIDIA's silicon bring-up and productization processes by developing methodologies, building test infrastructure, and managing global, cross-functional teams from pre-silicon through production.
Join NVIDIA's Silicon Solutions Group to lead post-silicon bring-up and system-level validation work that ensures performance, reliability, and successful product releases across GPU and SoC platforms.
Lead end-to-end board hardware architecture and validation for high-speed semiconductor platforms at Marvell’s Multimarket Business Group in Santa Clara.
Paid 12-week hardware engineering internships at NVIDIA offering hands-on projects in system validation, hardware design, mechanical engineering, or silicon solutions for students pursuing EE/CE or related degrees.
Senior HSIO Architect role focused on system-level high-speed I/O architecture, post-silicon validation, and cross-functional optimization for NVIDIA's GPU-accelerated platforms.
Lead validation architecture for next-generation NVLink interconnects, building models and driving test and integration efforts across pre- and post-silicon environments.
Lead validation and bring-up of high-speed mixed-signal and electro-optical interfaces at NVIDIA, developing tests, debugging silicon, and turning lab data into performance improvements.
Lead cross-functional silicon programs as a Senior Technical Program Manager driving SoC bring-up, validation, and productization at a market-leading semiconductor company.
Solidigm is hiring a TD Design Collateral Modeling Engineer to develop and calibrate device and interconnect models (SPICE/Verilog-A/RC) and partner cross-functionally to meet NAND performance and qualification goals.
Undergraduate interns will join Intel's Silicon Hardware Engineering teams in Hillsboro to help design, verify, and validate next-generation processor and SoC technologies.
Work with Intel's Silicon Hardware Engineering teams as an intern contributing to design, verification, validation and performance optimization of next-generation processors and platforms.
Marvell is hiring a Principal Digital Circuit Design Engineer in Burlington, VT to lead custom memory design, verification, and silicon characterization for advanced semiconductor products.
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