Job Details:

Job Description: 

We are seeking an exceptionally motivated and experienced Silicon Development Engineer to lead the architecture/micro-architecture definition and design of complex System-on-Chip (SoC) solutions. This role demands extensive understanding of SoC Architecture, Digital IP, and Network-on-Chip Interconnect design, coupled with significant pre/post-silicon debug expertise. The successful candidate will be instrumental in defining and implementing chassis architectures for advanced high-compute/performance SoCs.

Key Responsibilities:

• Lead architecture/micro-architecture definition for advanced high performance SoCs, including chiplet-based designs supporting high throughput die to die coherency. 
• Define and implement a scalable & high compute Chassis architecture for AI based consumer and server SoCs
• Drive micro-arch and design for high PPA solutions with optimised clock, reset, power for high compute SoC designs.
• Define end-to-end QoS solutions for multiple traffic class systems and implement low-latency, Head of Line blocking-free high throughput networks with complete freedom from interference
• Oversee SoC Chassis architecture, including Fabrics, SMMU & Access control
• Define Coresight compliant Debug and trace architecture for the chassis & SoC
• Work with design team to manage full-chip implementation of SoCs, encompassing Interconnect, SMMUs, Reset, Clocking, IO Mux, Debug-Trace, and High-Speed & Low speed IO Peripherals
• Work with Physical design teams to define the right SoC/Chassis partitioning, floor planning for a highly scalable SoC solution
• Drive project management, leading functional teams, and managing cross-functional multi-site projects.

Qualifications:

Minimum Qualifications

BS in electrical engineer or computer science with 12+ years of experience

8+ Years of in silicon development engineering, with a strong focus on complex SoC Architecture. 

5+ years of experience in experience in pre/post silicon debug.

5+ Years of  experience with Memory & High-Speed interfacing

Deep understanding of Full chip System bus/fabric architecture (Coherent & Non-coherent). 

Proven expertise in building SoCs with complex traffic class system with real time high throughput traffic management.

Strong background in Synthesis & Timing Analysis (Design Compiler/Primetime).

Experience with SOC Partitioning & Floor planning & strong awareness of technology nodes.

Preferred Qualifications

Strong understanding of latest DIE2DIE interfaces like UCIE & high-speed peripherals (PCIE) & Low speed peripherals (UART, SPI, CAN)

Solid knowledge of Multi-core infrastructure & IPC communication for efficient & performance SoC (looks good)

Proficiency with Simulation, Validation, and Signoff tools (IUS, Verdi, CDC, RDC, Lint).’’ (looks good)

Experience with 3nm chiplet-based SoC & chassis architecture.

Familiarity with UCIE based chiplet designs.

Hands-on experience with AMBA/CHI/UCIE/PCIE compliant High throughout interconnects.

Prior experience in leading microarchitecture and design for consumer/wireless/automotive/Server HPC SoCs.

Proven track record of defining and implementing low power, isolation & power management architectures.

Experience with third-party IP evaluation and liaison

Demonstrated experience in leading Digital IP teams and function lead roles.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Santa Clara

Additional Locations:

Business group:

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$204,500.00-$288,710.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.