Browse 6 exciting jobs hiring in Timing Analysis now. Check out companies hiring such as Cadence, NVIDIA, Intel in Laredo, Anchorage, Phoenix.
Experienced C/C++ software engineer needed to develop and optimize EDA physical design algorithms (CTS) at Cadence's Austin R&D team, with opportunities to apply AI/ML.
Lead development of AI-driven timing and constraint sign-off solutions that integrate timing tools, knowledge graphs, and agentic orchestration to accelerate sign-off on NVIDIA silicon.
Intel Central Engineering Group is hiring a Senior Silicon Design Engineer to lead RTL-to-GDS physical implementation, timing and power closure, and verification/signoff for complex SoC and IP designs.
AECOM is hiring a remote Traffic/ITS Engineer to deliver traffic analysis, ITS systems engineering, and technical design support across regional infrastructure projects.
Intel is hiring a technically strong CPU Backend Engineer to lead full-chip timing convergence, STA verification, and cross-functional collateral handoffs for future CPU designs.
Serve on NYC DOT's Signals, Timing, and Intersection Control Unit to conduct signal timing studies, implement APS/LPIs, and support Vision Zero and multimodal priority projects.
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