Senior/Staff Packaging Engineer - Electro-Thermal

Join the leading chiplet interconnect startup! We are seeking an experienced Senior/Staff Packaging Engineer specializing in electro-thermal simulation to join our advanced packaging team. You will develop comprehensive thermal and electrical simulations for next-generation semiconductor packaging solutions, including 2.5D/3D IC integration, chiplet-based systems, and advanced heterogeneous integration technologies. This role is critical in enabling high-performance computing, AI accelerators, and advanced chiplet architectures. We offer a fun work environment with excellent benefits. ONSITE M-F

•  Develop detailed thermal models for 2.5D/3D IC packages, chiplets, and multi-die systems; perform steady-state and transient thermal analysis with hotspot identification
• Execute power integrity (PI) and IR drop analysis; optimize power distribution networks (PDN) and power delivery architectures
• Conduct electromigration (EM) and reliability analysis for interconnects, bumps, TSVs, and redistribution layers (RDL)
• Develop chip-package co-simulation workflows using industry-standard EDA tools (ANSYS RedHawkSC, RHSC-ET, SIwave, Cadence Sigrity/Clarity)
• Create hierarchical compact macro models (CMM) and reduced-order thermal models for earlystage design optimization
• Automate simulation workflows using Python, TCL, and Shell scripting; build design space exploration tools
• Collaborate with silicon design, package design, and manufacturing teams on design-for-reliability (DFR) initiatives
• Support customer engagements with technical analysis and present findings to stakeholders

• PhD in Electrical/Mechanical Engineering, or related field with focus on thermal management, power delivery, or electronic packaging (Master's with 5+ years experience considered)
• Strong academic background in power integrity, signal integrity, and thermal management for advanced packaging

• Expert proficiency in: ANSYS RedHawk-SC, RHSC Electrothermal, Totem, PathFinder, SIwave, HFSS, Q3D; Cadence Voltus, Sigrity, Clarity; Synopsys RedHawk Fusion, PrimeTime, ICC2
• Experience with physical design tools (Cadence Innovus, Synopsys ICC2, Siemens Calibre) and RTLto-GDSII flows
• Strong programming/scripting: Python, C/C++, Tcl, Shell (bash); Verilog/VHDL/SystemVerilog for verification
• Knowledge of advanced packaging: 2.5D/3D ICs (CoWoS, InFO, EMIB), chiplets, TSVs, interposers, FOWLP, RDL design

• Deep understanding of EM/IR analysis, power integrity, thermal physics, and electrothermal cosimulation
• Expertise in heat transfer principles (conduction, convection, radiation), thermal material properties, and CTE mismatch
• Knowledge of chiplet standards (UCIe and BoW), die-to-die interfaces, and wafer-scale integration
• Hands-on experience with semiconductor package thermal/electrical analysis and tape-outs 

• Familiarity with machine learning applications in EDA and design optimization
• Experience with HPC, AI/ML accelerator packaging, or co-packaged optics (CPO)
• Background in reliability testing (thermal cycling, HTOL, THB) and measurement correlation

• Strong analytical mindset with expertise across multiple physics domains (thermal, electrical, mechanical)
• Excellent communication skills to present complex technical concepts to diverse audiences
• Cross-functional collaboration abilities to work with silicon, package, product, and manufacturing teams
• Self-motivated professional who thrives in fast-paced environments with minimal supervision
• Continuous learner staying current with emerging technologies; innovation-driven with creative problem-solving
• Results-oriented engineer delivering high-quality work to enable product milestones on schedule