Browse 18 exciting jobs hiring in Asic Design now. Check out companies hiring such as Marvell, NVIDIA, Jobgether in Grand Rapids, Fort Worth, Aurora.
Marvell seeks a senior Engineering IP Program Manager to lead mixed-signal and SoC IP development programs from specification through silicon validation and production.
Lead the architecture and technical direction for next-generation Ethernet and AI fabric networking solutions at NVIDIA, shaping high-performance interconnects for large-scale AI clusters.
Work with a fast-moving AI hardware team to design and optimize custom accelerators and SoC solutions that power next-generation machine learning systems.
Work on next-generation AI accelerators and SoC solutions, designing and optimizing hardware to power high-performance machine learning systems in a remote, collaborative environment.
Lead silicon architecture and delivery at Voyant Photonics as VP of Silicon Engineering, owning multi-project ASIC development from architecture through volume production to enable next-generation compact FMCW LiDAR.
Intel Central Engineering Group is hiring a Senior Silicon Design Engineer to lead RTL-to-GDS physical implementation, timing and power closure, and verification/signoff for complex SoC and IP designs.
NVIDIA is hiring a Senior Video ASIC Design Engineer to architect and implement video IP for next-generation SoCs, driving design quality and performance alongside cross-functional teams.
Work on the chip simulation team to design and maintain high-accuracy simulators and debugging tools that enable development of Etched's Sohu transformer ASIC software stack.
Senior Technologist to lead end-to-end ASIC/SoC development for SanDisk storage controllers, providing technical authority, risk management, and cross-functional leadership.
OpenAI’s Hardware team is hiring a Strategic Sourcing & Partnerships Manager to lead EDA/IP, emulation, and ASIC supplier strategy, contracting, and vendor partnerships for next-generation AI silicon.
Early-career CAD Engineer to drive standard cell development, automation, and DFM practices for NVIDIA's cutting-edge physical design teams in Santa Clara.
NVIDIA is hiring a Senior Package Layout Engineer to design and optimize high-speed, high-density ASIC package substrates in a hybrid Santa Clara role.
NVIDIA is hiring a Senior ASIC Physical Design Engineer (Netlisting) to drive netlist quality, equivalence checking, CDC analysis and timing closure for high-performance CPU/GPU/SoC designs.
NVIDIA is recruiting first- and second-year undergraduates for a 12-week, on-site Ignite Hardware Engineering internship in Santa Clara to work on real GPU, ASIC, and hardware infrastructure projects.
SpaceX is hiring a Physical Design Engineer to work on ASIC physical implementation and signoff for next-generation Starlink silicon.
Build high-performance ML compiler technology at Mythic to map deep learning workloads onto a novel analog dataflow accelerator while influencing hardware–software co-design.
Lead lab development and validation of LiDAR and camera imaging technologies for vehicle applications as an Advanced Optical Sensor Test Engineer at General Motors.
NVIDIA is hiring an EDA Workflow Optimization Engineer to investigate and optimize end-to-end chip-design workflows, build reliable metrics and infrastructure, and enable engineers to develop at high velocity.
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