ASIC Lead - Digital

Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed.

The Role

We’re searching for a ASIC Lead (Digital) who can drive a complex, high‑speed mixed‑signal chip from concept to mass production while line‑managing and mentoring a world‑class team of design engineers.

You will own delivery of the digital subsystems that stitch together > 100 high‑bandwidth lanes, interface to fast‑settling DACs and ADCs, and run deterministic control loops at > 100 MHz clock rates.

This is a hands‑on leadership position: you will manage and mentor a multidisciplinary team, own program execution to tape‑out, and serve as the principal technical authority for every digital block that underpins our OTPU.

Responsibilities

• Architect, plan and deliver the digital top level of a multi‑lane optical compute ASIC—RTL, synthesis, DFT/DFD, static‑timing and physical implementation.

• Lead cross‑functional teams (digital, analog, verification, layout, packaging, test, firmware) through all silicon lifecycle stages: architecture ► spec ► RTL ► physical design ► sign‑off

• Lead and line‑manage 6‑12 digital & mixed‑signal engineers: goal‑setting, performance reviews, recruiting, and skills development and maintain a culture of rapid, first‑time‑right design.

• Define and track project schedules, budgets and risk‑mitigation plans; present status, trade‑offs and escalation options to executives and customers.

• Collaborate with analog leads on fast‑settling current‑steering DACs, high‑speed SerDes, PLLs and clock‑mesh networks to guarantee end‑to‑end timing determinism and low‑latency control loops.

• Drive design verification strategy—UVM test‑benches, gate‑level sims, FPGA prototyping—and own silicon bring‑up test plans that hit first‑silicon functional goals.

• Optimise multi‑lane protocols for bandwidth scaling, skew management and power efficiency; integrate error monitoring, calibration engines and field‑update hooks.

• Encourage a culture of continuous improvement—methodology automation, design‑flow enhancements, documentation and knowledge sharing.

Skills & Experience

• 12 + years of digital ASIC development, with at least 3 full product cycles taken from specification through volume production.

• Demonstrated success leading a digital team that delivered high speed ASICs containing high‑speed mixed‑signal interfaces (display drivers, image sensors, SerDes, RF SoCs, etc.).

• Strong command of RTL design (SystemVerilog / Verilog), CDC/RDC, STA, place‑and‑route, power intent (UPF/CPF) and DFT/DFD methodologies.

• Demonstrated success coordinating multi‑lane data paths, clock distribution and fast‑settling DAC / ADC control loops while closing timing and power at advanced nodes.

• Solid understanding of mixed‑signal interaction: coupling, jitter, supply‑noise and on‑chip calibration; able to read analog schematics and agreeing specification splits.

• Experience with high‑speed display or camera pipelines—timing controllers, MIPI / DSI / CSI, LVDS, DisplayPort, HDMI, or similar—strongly desired.

• Prior people‑management responsibility: hiring, mentoring, salary planning and performance management for engineers.

• Excellent project‑leadership skills: schedule ownership, risk analysis, vendor/foundry engagement, first‑pass success mindset.

• Outstanding written and verbal communication; comfortable presenting detailed technical and program status to executives, customers and cross‑site teams.

Frequent travel is expected between our Austin and London offices.

We’re building fast and that includes our benefits. More exciting additions are coming soon for the Flux crew.

If you are passionate about pushing the boundaries of what's possible in AI and thrive in a high-energy, fast-paced environment, we want to hear from you. Apply now to join Flux and be a key player in shaping the future of computing.