Work closely with RTL Designers to understand hardware blocks in depth to go through the
architecture and of the overall design. Write test plans that comprehensively cover different aspects
of the design to develop test environments that implement the test plans as well as develop unit
level and chip level testbenches to test the design at different granularities. Develop testbench and
testbench components (Ex: irritators, stallers etc) using SystemVerilog to perform verification of
different hardware blocks. Write checkers and monitors using C++ to validate the functioning of the
RTL design, and maintain the DV infrastructure to improve the efficiency and productivity of the
team by writing scripts in Python and Shell. Launch and monitor regressions to capture the progress
in the design verification process, and contribute positively to the company's codebase and help in
the code review process for fellow team members.
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