Browse 11 exciting jobs hiring in Cpu now. Check out companies hiring such as NVIDIA, Rivos, Aarons in Little Rock, Denver, Oakland.
At NVIDIA, apply formal verification expertise and cutting-edge LLM/agent technologies to validate complex GPU/CPU designs and build production AI tooling that speeds verification and debugging.
Work on microarchitecture and logic design verification for a CPU team, building testbenches and verification infrastructures using SystemVerilog, C++, and Python to validate functionality and performance.
Rivos seeks a Silicon Power Engineer to lead power modeling, analysis, and optimization across CPU/SoC blocks, partnering closely with architecture and design teams to drive PPA improvements.
A paid, full-time 12-week hardware verification internship at NVIDIA in Santa Clara for students pursuing degrees in electrical or computer engineering to work on real verification and validation projects.
Senior Technical Program Manager at NVIDIA responsible for leading cross-functional programs to scale, modernize, and operationalize the EDA infrastructure that supports chip bringups and production flows.
NVIDIA is hiring a Senior Circuit Design Engineer to lead power delivery network modeling and simulation across die-to-platform designs and mentor junior engineers in a hybrid Santa Clara role.
Lead microarchitecture and RTL development for power management and debug features at Rivos, working across SoC teams to deliver high-performance, power-efficient RISC-V server solutions.
Lead cross-functional teams to deliver and commercialize Tenstorrent's RISC-V IP, ensuring smooth customer adoption and world-class technical delivery.
Work on RTL and micro-architecture for AI/ML and data-analytics accelerators, using SystemVerilog, architecture insight, and synthesis/physical-design awareness to deliver high-performance, low-power designs.
Work with Intel's Silicon Hardware Engineering teams as an intern contributing to design, verification, validation and performance optimization of next-generation processors and platforms.
Drive physical design and static timing analysis to achieve timing closure on high-performance ASICs (GPUs/CPUs/SoCs) at NVIDIA's Santa Clara engineering team.
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