Timing Jobs
Browse 26 exciting jobs hiring in Timing now. Check out companies hiring such as NVIDIA, AECOM, Jobgether in San Francisco, Columbus, Orlando.
NVIDIA seeks new college graduates for an ASIC Design Engineer role contributing RTL, micro-architecture and verification work on GPUs and SoCs.
AECOM is hiring a California Traffic Engineering State Manager to lead traffic engineering teams, projects, and business development across Orange, Oakland and Los Angeles offices on a hybrid schedule.
Lead the design and delivery of customer-facing FPGA solutions and reference platforms, translating complex requirements into system-level hardware and software architectures across AI/ML, datacenter, networking, and industrial markets.
Lead the architecture, RTL implementation, simulation, and verification of FPGA/ASIC solutions for high-reliability electronic control systems in a hybrid role requiring U.S. citizenship.
Experienced electro-optical engineer needed to lead sustainment, test, and integration activities for NSGN SLR/VLBI ground systems supporting space programs.
Lead the technical design and customer-facing delivery of FPGA-based system solutions, shaping product roadmaps and demonstrating use cases across multiple markets.
NVIDIA is hiring a VLSI CAD Engineer in Santa Clara to develop and maintain scalable EDA/CAD flows and automation that speed development of next-generation AI chips.
Syntiant is hiring a seasoned SoC Design Engineer to drive microarchitecture, RTL implementation, verification, low-power design and silicon bring-up for the next-generation Neural Decision Processor.
Senior FPGA/ASIC engineer needed to architect and verify complex RTL-based designs for high-reliability electronic control systems in a hybrid U.S. role requiring citizenship.
NVIDIA seeks a Senior System Integration Engineer to lead post-silicon system bring-up, debug, and validation for next-generation GPU and SoC products.
AECOM is hiring a Traffic/ITS Engineer in Denver (hybrid) to lead traffic analysis, ITS systems work and design deliverables for regional infrastructure projects.
Drive transistor-level timing analysis and custom macro validation at NVIDIA as a Senior Circuit Engineer specializing in Custom Timing.
Lead the design and implementation of GPU-first EDA algorithms for IR drop, timing, and power modeling at NVIDIA, leveraging CUDA and advanced parallel techniques to transform physical design workflows.
An Irvine-based semiconductor team needs a Senior STA Physical Design Engineer to lead STA closure, SI/PI work, and chip finishing for complex digital SoCs with a hybrid remote/onsite arrangement.
Lead and grow LaBella’s traffic engineering practice across Long Island and the NYC metro as a senior technical lead, client advisor, and business development driver working hybrid or remotely.
Kickstart Entertainment seeks an experienced Storyboard Revision Artist to efficiently deliver polished storyboard revisions and new sequences for a 3D animated series in a hybrid studio/remote role.
Taara Connect is hiring an FPGA Design Engineer to design, verify, and bring up high-speed FPGA logic for optical communications and precision tracking systems.
Rambus seeks a New College Grad Digital Design Engineer (AMTS) to help develop memory and silicon IP through RTL design, ASIC flow work, and verification in a hybrid, team-oriented engineering environment.
NVIDIA is seeking a Senior ASIC Power Engineer to lead power-optimization and RTL delivery for high-performance GPU and system-on-chip designs across mobile, embedded and datacenter platforms.
Join NVIDIA's Silicon Solutions Group to lead post-silicon bring-up and system-level validation work that ensures performance, reliability, and successful product releases across GPU and SoC platforms.
Lead RTL-driven FPGA design and system bring-up for a security-focused hardware platform at a fast-growing Silicon Valley company.
NVIDIA is hiring a Senior Digital Design Engineer to drive front-end RTL/firmware development, synthesis and timing closure, and post-silicon bring-up for high-speed I/O and silicon photonics products.
Contribute to NVIDIA's hardware teams as a 12-week Hardware Physical Design / VLSI intern, working on synthesis, timing, floorplanning, and EDA tool flows that impact real chip projects.
NVIDIA is hiring a Senior Circuit Design Engineer to lead transistor-level and custom digital IP design for cutting-edge GPU and AI products.
Lead digital PCBA architecture, design, and flight development for cutting-edge LEO satellite systems at a fast-moving space communications startup.
Contribute to NVIDIA’s hardware ASIC teams on a 12-week, full-time internship building and verifying RTL and physical-design solutions for next-generation accelerated computing products.
How much do timing jobs pay?
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Over 100k*
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