Timing Jobs
Browse 23 exciting jobs hiring in Timing now. Check out companies hiring such as AECOM, Red 6, NVIDIA in Plano, Mobile, Tulsa.
AECOM is hiring a Civil Engineering II in Chicago to perform traffic/ITS analyses, modeling and design support on transportation projects while adhering to industry standards and project budgets.
Lead FPGA design and verification efforts for Red 6's ATARS product, applying deep FPGA expertise to high-speed interfaces, timing closure, and system integration in a fast-paced aerospace environment.
Drive physical design and static timing analysis to achieve timing closure on high-performance ASICs (GPUs/CPUs/SoCs) at NVIDIA's Santa Clara engineering team.
Kimley-Horn seeks an experienced Civil EIT in Indianapolis to perform traffic engineering analyses, manage project tasks, mentor staff, and contribute to business development within a collaborative transportation team.
Field AI is hiring a Sensor Systems Engineer to design, integrate, calibrate, and validate multi-sensor perception systems (LiDAR, depth cameras, IMUs, GPS) for real-world autonomous robots.
Lead FPGA Engineer to architect and deliver high-performance multi-FPGA designs and lead the FPGA engineering team for Red 6's AR-based training systems.
Lead and grow a local Transportation/Traffic practice in Daytona Beach as a Senior Project Manager with strong technical, business development, and leadership responsibilities at Kimley-Horn.
Lead and deliver transportation and traffic engineering projects in Kimley-Horn's Atlanta office, combining technical practice, project management, and business development.
AECOM is hiring a Senior Traffic Engineer in Los Angeles to lead California traffic engineering projects, coordinate with LADOT/Caltrans, and mentor junior engineers.
Expert Physical Design Engineer needed to drive RTL2GDS implementation of high-performance LiDAR SoCs at Aeva.
Experienced Physical Design Engineer needed at Sandisk to lead synthesis, PNR, STA, and related digital physical design efforts in Milpitas, CA.
Lead the architecture and design of advanced high-performance SoCs at Intel’s CTO AI Group, driving innovation in AI silicon solutions.
Advanced semiconductor firm seeks Senior Engineer to lead GPU micro-architecture and RTL design efforts with a hybrid work model based in Austin, TX.
Contribute to next-generation CPU designs as a Physical Design Engineer intern at Intel, driving innovation within their Xeon Engineering Group.
Broadcom is hiring an IC Design Engineer with expertise in layout design and timing closure to advance AI compute core technologies.
Broadcom is hiring an experienced RTL Synthesis Engineer skilled in advanced optimization, synthesis, and verification methodologies to enhance data center connectivity solutions.
Intel is looking for an experienced SoC Micro-Architect to lead feature implementation and micro-architecture design for high-performance SoC products.
Lead the micro-architecture and RTL design of cutting-edge AI compute hardware at d-Matrix, fostering innovation in generative AI technology.
Experienced GPU SOC Design Engineer needed at Intel to lead RTL logic design and integration for discrete graphics SoCs in an on-site role.
Senior/Staff Digital Design Engineer needed at Flux Computing to drive high-performance CMOS digital design for next-generation AI hardware.
Drive timing closure and workflow automation as a CPU Design Timing Engineer at Apple, working closely with micro-architects and implementation teams.
A seasoned ASIC/FPGA Engineer is needed at General Dynamics Mission Systems to lead design and verification of high-reliability defense electronics in a hybrid work setting.
Lead micro-architecture and RTL design for cutting-edge AI control subsystems at d-Matrix, a forward-thinking generative AI technology company.
How much do timing jobs pay?
Below 50k*
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50k-100k*
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Over 100k*
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