Browse 10 exciting jobs hiring in Timing now. Check out companies hiring such as Intel, City and County of San Francisco, FM in Peoria, Minneapolis, San Jose.
Lead RTL development and SoC-level IP integration as a Principal Engineer in Intel's Client Engineering Group, shaping architecture, verification, and delivery across CPU/GPU/NOC and advanced compute projects.
SFMTA is recruiting engineering interns for Summer 2026 to support transportation planning, design, and operations projects across Streets and Transit divisions while gaining field experience and professional development.
Drive RTL-to-GDS physical implementation and signoff for custom Xeon-based SoCs in Intel's Data Center Group, focusing on timing closure, power optimization, and manufacturability.
NVIDIA is hiring an ASIC Design Engineer to build and maintain hardware design tools, automated RTL generation workflows, and verification methodologies that scale across product teams.
Senior ASIC Design Engineer to develop high-performance, low-latency Switch Silicon RTL and deliver production-ready, timing-clean designs at NVIDIA's Santa Clara engineering team.
Contribute to the design and implementation of high-performance, low-power CPUs at NVIDIA’s Hillsboro team, supporting AI, automotive, and consumer products.
Experienced traffic engineering leader needed to manage complex signal, corridor timing, and traffic operations projects while growing client relationships and mentoring a design team at AMT's Charleston office.
Experienced C/C++ software engineer needed to develop and optimize EDA physical design algorithms (CTS) at Cadence's Austin R&D team, with opportunities to apply AI/ML.
Marvell seeks a senior Engineering IP Program Manager to lead mixed-signal and SoC IP development programs from specification through silicon validation and production.
NVIDIA is hiring a Senior ASIC Design Engineer (Clocks IP) to design and deliver robust, high-performance clocking solutions for next-generation GPU and CPU chips.
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