Risc V Jobs

Technical Program Manager to lead cross-functional hardware and software programs at Tenstorrent, driving schedules, risks, and cross-team alignment for high-performance AI products.

Rivos seeks a Silicon Power Engineer to lead power modeling, analysis, and optimization across CPU/SoC blocks, partnering closely with architecture and design teams to drive PPA improvements.

Customer-Centric

Mission Driven

Inclusive & Diverse

Rise from Within

Diversity of Opinions

Work/Life Harmony

Growth & Learning

Transparent & Candid

Medical Insurance

Paid Time-Off

Maternity Leave

Mental Health Resources

Equity

Child Care stipend

Paternity Leave

WFH Reimbursements

Flex-Friendly

Dental Insurance

Vision Insurance

Life insurance

Health Savings Account (HSA)

Flexible Spending Account (FSA)

401K Matching

Military leave

Drive compiler verification at NVIDIA by designing modern C++ testsuites, automating test frameworks, and improving coverage using advanced techniques including LLM-assisted testing.

Rivos Inc. is hiring an experienced SoC Fabric Architect to lead architecture and specification of on-chip and off-chip interconnects, cache-coherent and non-coherent protocols, and system-level fabric trade-offs for high-performance RISC-V platforms.

Lead microarchitecture and RTL development for power management and debug features at Rivos, working across SoC teams to deliver high-performance, power-efficient RISC-V server solutions.

Tenstorrent seeks a Sr Staff Software Engineer to lead toolchain and compiler development for its RISC‑V AI processors, focusing on code generation, optimization, and robust toolchain infrastructure.

Lead cross-functional teams to deliver and commercialize Tenstorrent's RISC-V IP, ensuring smooth customer adoption and world-class technical delivery.

Work on multi-FPGA, low-latency hardware systems at Riverlane to implement QEC decoders, high-throughput data movement and low-latency interfaces as a Digital Design Engineer.

Mission Driven

Social Impact Driven

Passion for Exploration

Reward & Recognition

Lead embedded software development for Starlink customer hardware at SpaceX’s Bastrop facility, writing robust Linux and low-level code for devices deployed to millions of users.

Senior Digital Design Engineer role at Riverlane to develop advanced quantum error correction hardware IPs within a collaborative hybrid work environment.