Browse 10 exciting jobs hiring in Chip now. Check out companies hiring such as MLabs, NVIDIA, FM in Anchorage, Baton Rouge, Yonkers.
Lead the AI roadmap and a growing ML team at a Palo Alto startup building agentic systems that speed up semiconductor design through RTL code generation and physical-design optimization.
NVIDIA is hiring an EDA Workflow Optimization Engineer to investigate and optimize end-to-end chip-design workflows, build reliable metrics and infrastructure, and enable engineers to develop at high velocity.
Senior Software Engineer to design and implement high-performance C++/Golang tools for code analysis, coverage, and chip verification at NVIDIA's Santa Clara engineering organization.
Senior Design Verification Engineer needed to lead digital ASIC verification for Starlink's next-generation space and ground chips at SpaceX's Sunnyvale engineering team.
Experienced ASIC design verification engineer needed to lead block- and system-level verification for Starlink ASICs, supporting pre-silicon verification through post-silicon validation at SpaceX.
An Irvine-based semiconductor team needs a Senior STA Physical Design Engineer to lead STA closure, SI/PI work, and chip finishing for complex digital SoCs with a hybrid remote/onsite arrangement.
Lead the design and deployment of agentic LLM-based systems at NVIDIA to accelerate and innovate chip architecture and engineering workflows.
Rambus is hiring an RTL Digital Intern to design SystemVerilog RTL and support chip integration and verification for high-performance memory interface products.
Contribute to NVIDIA's hardware teams as a 12-week Hardware Physical Design / VLSI intern, working on synthesis, timing, floorplanning, and EDA tool flows that impact real chip projects.
Technical leader needed to manage and grow a multidisciplinary mixed-signal ASIC design team delivering EO/IR sensor chips and camera integration for demanding aerospace applications.
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