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Senior Silicon Application Engineer (Packaging Design)

Job Details:

Job Description: 

About Intel Foundry Services

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

Position Overview

We seek a highly motivated, results-driven Senior Silicon Applications Engineer (Packaging Design) to join our team within Intel Foundry Aerospace, Defense and Government (ADG). This role focuses on advanced packaging technologies, working closely with foundry customers to define, develop, and implement design tools, flows, and methodologies for system co-design, implementation, and verification. You will serve as the technical expert on packaging design tools while consulting on design and implementation challenges.

Key Responsibilities

Customer Technical Leadership

  • Establish technical credibility, building trust and strong relationships with Intel Foundry ADG customers
  • Ensure customers successfully evaluate, adopt, and design products using Intel process technology
  • Serve as primary technical expert on packaging design tools and implementation methodologies
  • Provide clear communications and technical guidance to customers and stakeholders
  • Analyze customer design issues and environments to define functional specifications for EDA vendors
  • Drive adoption of advanced packaging verification methodologies including signal integrity and power integrity

Advanced Packaging Solutions

  • Work closely with customers on advanced packaging technologies including multi-die/3DIC platforms
  • Support design implementation and verification across complex packaging architectures
  • Consult on packaging design challenges and provide innovative technical solutions

Cross-Functional Collaboration

  • Synthesize complex technical information and lead in-depth tactical discussions with customers
  • Collaborate with Intel engineering teams to address customer requirements and technical challenges
  • Support customer evaluations and design reviews for advanced packaging implementations
  • Drive results through highly organized, analytical approach and strong teamwork

Core Competencies

  • Strong technical credibility and customer relationship building skills
  • Highly organized, analytical mindset with strong team collaboration abilities
  • Excellent communication skills for complex technical discussions
  • Results-driven approach with ability to deliver customer success outcomes

Qualifications:

The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

  • US Citizenship required
  • Ability to obtain US Government Security Clearance
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field
  • 7+ years of experience in Package Design and relevant EDA tools
  • Experience interfacing with customers and/or stakeholders
  • Experience analyzing customer design issues, environments, and defining functional specifications for EDA vendors

Preferred Qualifications

  • Active US Government Security Clearance with a minimum of Secret Level.
  • Post-graduate degree in Electrical/Computer Engineering or STEM-related field
  • Experience with Advanced EDA Tool
  • Experience with Multi-die/3DIC Platform Tools: Cadence Integrity, Synopsys 3DIC Compiler, Siemens Xpedition Substrate Integrator/Innovator 3D
  • Experience with Implementation Tools: Cadence Virtuoso/Innovus, Allegro (APD/SiP), Siemens Mentor Xpedition, Synopsys Fusion Compiler
  • Experience with Verification Tools: Siemens Calibre, Synopsys ICV, Cadence Pegasus
  • Experience with design for verification and performance including Package Signal Integrity, Power Integrity, manufacturing, and yield optimization
  • Proficiency in scripting languages (Tcl, Python, SKILL, VBScript) for design flow automation and efficiency improvements
  • Deep understanding of advanced packaging architectures and system-level design challenges

What We Offer

  • Opportunity to work on cutting-edge advanced packaging technologies for aerospace, defense, and government applications
  • Direct customer engagement and technical leadership role
  • Access to Intel's most advanced foundry technologies and EDA tool suites
  • Competitive compensation
  • Professional development in advanced packaging and foundry services
  • Direct impact on Intel's foundry business growth and customer success

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

US, California, Santa Clara, US, Oregon, Hillsboro

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$238180 / YEARLY (est.)
min
max
$164470K
$311890K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

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BADGES
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CULTURE VALUES
Inclusive & Diverse
Rise from Within
Mission Driven
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Customer-Centric
BENEFITS & PERKS
Snacks
Onsite Gym
Family Coverage (Insurance)
Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Resources
Life insurance
Disability Insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
Learning & Development
Paid Time-Off
401K Matching
Maternity Leave
Paternity Leave
FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
EMPLOYMENT TYPE
Full-time, hybrid
DATE POSTED
January 11, 2026
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