SerDes Design Validation Engineer

In this role you will contribute to the design, integration and validation of high-performance analog and mixed-signal circuits for SerDes PHY applications. This encompasses the design and optimization of critical building blocks such as receivers, transmitters, bias generators, high-speed clock generation and distribution networks targeting best-in-class power, performance, and area metrics. A key part of your design responsibilities will include the development of analog DFT circuits and techniques essential for comprehensive PHY validation. You will develop test plans, review and analyze data to guarantee a robust IP design. You will drive and work closely with production test (e.g. ATE, system validation) teams and debug complex design and system bring-up issues.

Description

You will collaborate closely with cross-functional teams including architecture, RTL design, verification, signal integrity, packaging, board design, DFT and ESD to ensure seamless PHY integration, feature verification and power delivery. This position offers substantial technical leadership opportunities and a direct impact on the development of next-generation high-speed connectivity solutions. You will thrive in a collaborative environment, engaging regularly with peers and management, fostering innovation, technical growth and career development.

Minimum Qualifications

BSEE with 10+ years of proven experience.

Preferred Qualifications

PhD in Electrical Engineering with 7+ years of experience or MSEE with 10+ years of experience. Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters. Solid understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques. Solid understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops). Hands-on experience to drive lab and production testing, debug, and data analysis Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization. Skills in scripting and automation to enhance efficiency are highly desirable. Experience in high-speed serial links, with knowledge of common high-speed SerDes protocols like PCIe, USB, DP, and MPHY. Knowledge of Tx/Rx equalization techniques and circuits, including CTLE, DFE, and de-emphasis, as well as CDR architectures and implementations. Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired. Exposure to firmware assisted mixed signal IP development is desirable. Knowledge and inquisitiveness in AI/ML domains, and ability to apply the concepts for improved silicon performance, and also for productivity improvements in the design/validation of the IP.