Wafer Jobs

SRI International seeks a hands-on Test Engineer I in Princeton to develop and run ATE-based characterization and QML screening for microcircuits supporting trusted foundry manufacturing.

Process Engineer opportunity at the Texas Institute for Electronics to develop and execute advanced semiconductor fabrication and integration processes in a dynamic research cleanroom.

Atomic Semi is seeking a hands-on Process Engineering Intern in San Francisco to design experiments, process wafers, and analyze results while helping build a small, fast semiconductor fab.

Texas Institute for Electronics is hiring a Facilities Control Engineer I or II to design, program, and maintain PLC/SCADA control systems for critical fab utility systems in Austin.

Lead and develop the Fremont facilities engineering and maintenance team to ensure reliable 24/7 wafer-fab operations, driving maintenance strategy, capital projects, and regulatory compliance for critical infrastructure.

Experienced equipment engineer needed to lead sustaining and upgrade efforts for vacuum ion beam etch/deposition systems in Western Digital's San Jose wafer fabrication environment.

Lead lithography process development and yield optimization for Western Digital’s wafer manufacturing, driving improvements across coat, expose, and develop steps and implementing SPC/APC strategies.

Mission Driven

Social Impact Driven

Passion for Exploration

Reward & Recognition

SpaceX's Akoustis subsidiary is hiring an onsite RF Test Engineer to develop and sustain automated probe and VNA test processes for BAW RF filters in a high-volume manufacturing environment.

Begin your career as an Entry Level Equipment Engineer at NXP, maintaining and improving wafer fab equipment and process controls to drive yield, reliability, and capacity in the Austin fab.

Rambus is hiring a Test Engineering Intern in San Jose to support DFT, wafer-sort, first-silicon bring-up, and test program development for advanced memory and silicon IP products.

Solidigm is hiring a Package Architect to lead advanced SSD/NAND package design and signal-integrity driven architecture at its Rancho Cordova headquarters.