Cadence Allegro Jobs

Experienced PCB Layout Engineer needed to design complex HDI rigid and rigid-flex SSD PCBs (DDR/PCIe/NAND routing) using Cadence Allegro, collaborating with global engineering and vendor teams to deliver manufacturable ODB++/Gerber outputs.

Lead end-to-end board hardware architecture and validation for high-speed semiconductor platforms at Marvell’s Multimarket Business Group in Santa Clara.

Lead end-to-end hardware circuit pack design and validation at Ciena, delivering high-speed, production-ready PCB solutions in collaboration with multidisciplinary teams.

Renesas is seeking a Senior ESD and Latch-up Engineer in Palm Bay to lead characterization, testing, and debug of ESD and latch-up behavior for semiconductor products.